Electrical Engg (EEE) - MCQ Practice Questions

AND gate outputs HIGH only when all inputs are HIGH. This is its fundamental definition.

A single NAND gate with both inputs tied together acts as a NOT gate (inverter).

When J=1 and K=1, the J-K flip-flop toggles its state on each clock pulse.

A 3-to-8 decoder has 3 input lines and 2^3 = 8 output lines, one for each possible input combination.

Setup time is the minimum duration that input data must remain stable before the active clock edge for proper capture by the flip-flop.

A 5-variable K-map requires 2^5 = 32 cells, typically arranged as two 4x4 grids representing the fifth variable's 0 and 1 states.

For n select lines, 2^n output lines are possible. Here 2^4 = 16, so 4 select lines are needed. This is a standard 16:1 multiplexer.

BCD represents decimal digits 0-9 using 4 bits. A single BCD counter counts from 0 to 9, after which it resets.

CMOS has virtually zero static power consumption because complementary transistors prevent direct paths from supply to ground in steady state.

For n input variables, truth table rows = 2^n. For 6 inputs: 2^6 = 64 rows.

A 3-to-8 decoder requires 8 output lines. Each output is active for one unique combination of 3 inputs, requiring 8 AND gates, each with 3 inputs (one for each input variable or its complement).