Which of the following Boolean expressions is equivalent to (A+B)·(A+C)?
Answer: A
Using distribution law: (A+B)·(A+C) = A + BC (Consensus theorem verification)
Q.2Hard
In a 3-bit binary counter with initial state 000, after 9 clock pulses, the state will be:
Answer: A
3-bit counter is MOD-8. After 8 pulses it returns to 000, so after 9 pulses state is 001 (counts 0-7, repeats)
Q.3Hard
Design a circuit using NAND gates only to implement NOR function. How many NAND gates are minimum required?
Answer: B
NOR(A,B) = NAND(NAND(A,A), NAND(B,B)). First two gates provide inverted inputs, third performs NAND operation
Q.4Hard
A decade counter counts from 0 to 9. To design a decade counter from a binary counter, how many flip-flops minimum are needed along with additional logic?
Answer: B
4 flip-flops can count 0-15 (MOD-16). With reset logic at count 10, it becomes MOD-10 (decade counter)
Q.5Hard
A full adder can be implemented using how many NAND gates minimum?
Answer: C
A full adder requires 9 NAND gates minimum when implemented using NAND gates exclusively to realize the sum and carry outputs.
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Q.6Hard
In a Gray code counter, consecutive counts differ by exactly:
Answer: A
Gray code is designed such that consecutive values differ in exactly one bit position, reducing transition errors in digital systems.
Q.7Hard
In a synchronous counter design, all flip-flops receive the clock signal simultaneously. This arrangement primarily eliminates:
Answer: A
Synchronous counters eliminate propagation delay accumulation and race conditions by clocking all flip-flops simultaneously, enabling higher frequency operation.
Q.8Hard
A Schmitt trigger input is used in digital circuits primarily to:
Answer: B
Schmitt trigger provides hysteresis (different thresholds for rising/falling edges), effectively eliminating noise-induced multiple transitions on slowly changing inputs.
Q.9Hard
When implementing a 3-variable Boolean function using a 2-to-1 multiplexer instead of a 8-to-1, one variable must be:
Answer: C
A 2-to-1 MUX has only 1 select line (covering 2 input combinations). For 3 variables (8 combinations), the third variable must be processed through additional logic gates and distributed between select and data paths.
Q.10Hard
What is the hold time constraint violation in sequential circuits?
Answer: A
Hold time violation occurs when input data changes before the hold time window after the clock edge, corrupting the captured data.
Q.11Hard
Which digital logic family provides the best balance between speed and power consumption?
Answer: B
CMOS offers optimal trade-off with low static power dissipation and moderate switching speeds suitable for most applications.
Q.12Hard
In a 4-bit BCD adder, what is the maximum sum that can be represented without requiring correction?
Answer: C
In BCD addition, a result of 18 (binary 10010) requires correction code to convert to valid BCD (1000 + carry). Sums up to 9+9=18 need correction when exceeding 9.
Q.13Hard
What is the primary function of a state machine in digital design?
Answer: B
State machines control digital circuits by transitioning through defined states based on current state, inputs, and clock signals, implementing complex logic sequences.
Q.14Hard
In a 8-bit barrel shifter, how many control bits are required to specify any shift amount?
Answer: B
For an 8-bit barrel shifter, 3 control bits can specify 2^3 = 8 different shift positions (0 to 7), covering all possible shifts.
Q.15Hard
In a sequential logic circuit, metastability occurs when the input changes relative to the clock edge. How can this be minimized?
Answer: B
Synchronizer circuits use cascaded flip-flops to provide settling time between asynchronous signal and sampling clock, reducing metastability risk.
Q.16Hard
In asynchronous sequential circuits, what is the primary concern regarding state transitions?
Answer: B
Asynchronous circuits lack global clock, so multiple state variables can change simultaneously, causing race conditions and hazards if not carefully designed.
Q.17Hard
In the context of digital signal processing, what is the Nyquist sampling theorem's requirement?
Answer: B
Nyquist theorem states fs ≥ 2×fmax to avoid aliasing. Sampling below this rate causes frequency components to fold back and corrupt the signal.
Q.18Hard
In a synchronous counter design using SR flip-flops with Karnaugh map minimization, which hazard is most critical in the implementation?
Answer: C
Both static hazards (output glitches) and dynamic hazards (multiple transitions) can occur in combinational logic of counter design. Proper K-map grouping and implementation techniques are needed to minimize them.
Q.19Hard
What is the setup time requirement for a D flip-flop in a shift register operating at 100 MHz clock frequency?
Answer: D
Setup time is a manufacturer-specified parameter that varies by IC type and technology. At 100 MHz (10 ns period), typical setup times range from 2-5 ns, but exact requirements must be verified from the datasheet. General frequency calculation alone cannot determine setup time.
