Electrical Engg (EEE) - MCQ Practice Questions

A D flip-flop captures the input data on the rising edge of the clock pulse and transfers it to the output Q.

Flash ADC uses parallel comparators and provides the fastest conversion as it converts in a single clock pulse, though at higher cost and power consumption.

A decade counter divides the input frequency by 10. Output frequency = 1 MHz ÷ 10 = 100 kHz.

Setup time is the minimum time before the active clock edge during which the input data must remain stable to ensure correct capture.

ECL (Emitter Coupled Logic) has the highest power dissipation among standard logic families but offers excellent speed performance.

For 16 inputs, select lines required = log₂(16) = 4. These 4 lines can produce 2⁴ = 16 unique combinations.

In ripple counters, each flip-flop triggers the next, causing cumulative delay. Total delay = n × tₚ, limiting maximum frequency.

A Parallel-In-Serial-Out (PISO) shift register accepts parallel data and outputs it serially, bit by bit.

A·B + A·B' = A(B + B') = A·1 = A (using factoring and complement law)

Hold time is the minimum duration data input must remain stable after the active clock edge.

A 32:1 MUX requires 8 4:1 MUXes in first stage ($\frac{32}{4}$=8) and 2 4:1 MUXes in second stage, totaling 10. However, using 6 4:1 MUXes is an efficient hierarchical implementation with proper decoding.

T (toggle) flip-flop is ideal for frequency division as it divides input frequency by 2 when toggling.

8-bit 2's complement range is from -2^7 to 2^7-1, which is -128 to +127.

CMOS has minimal static power consumption (only during switching), making it ideal for battery-powered devices.

4GB = 4 × 2^30 bytes = 2^32 bytes. Therefore, 32 address lines are needed (2^32 addresses).

Priority encoders are designed with built-in priority logic where the highest priority input (usually MSB) is encoded when multiple inputs are active.

Gray code ensures only one bit changes between consecutive values, reducing errors in digital transitions and rotary encoders.

Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delays that cause glitches in asynchronous designs.

CMOS logic has noise margins typically around 30-40% of supply voltage, superior to TTL (~0.4V) and ECL (~0.2V).

De Morgan's law states: (A.B)' = A'+B' (NAND equals OR of inverted inputs) and (A+B)' = A'.B' (NOR equals AND of inverted inputs).