Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
Which of the following is a sequential logic circuit?
Answer: C
Flip-flops are sequential logic circuits with memory; others are combinational circuits without memory
Q.2Medium
In a JK flip-flop, when J=1 and K=1, the next state will be:
Answer: C
JK flip-flop truth table: J=1, K=1 causes toggle (Q switches to Q', Q' switches to Q)
Q.3Medium
What is the fan-out of a logic gate?
Answer: B
Fan-out specifies how many standard loads (inputs of similar gates) one output can drive without degradation
Q.4Medium
Which digital logic family has the highest speed of operation?
Answer: C
ECL (Emitter Coupled Logic) has propagation delay ~1ns, fastest among families despite higher power consumption
Q.5Medium
The number of logic levels required to represent 32 different states in binary is:
Answer: B
2^n = 32, therefore n = 5 bits (since 2^5 = 32)
Q.6Medium
What is the main advantage of CMOS logic over TTL?
Answer: B
CMOS technology draws power only during switching, resulting in very low static and dynamic power consumption compared to TTL
Q.7Medium
A 4-to-1 multiplexer has inputs A, B, C, D and select lines S₁, S₀. If S₁=0 and S₀=1, which input is selected?
Answer: B
Selection code 01 (binary) = 1 (decimal), which selects input B (second input)
Q.8Medium
In Karnaugh map simplification, a group of 8 adjacent cells eliminates how many variables?
Answer: C
A group of 2^n cells eliminates n variables. Group of 8 = 2^3, eliminates 3 variables
Q.9Medium
What is the primary function of an encoder in digital electronics?
Answer: C
Encoder produces binary-coded output corresponding to only one active input line among many inputs
Q.10Medium
A synchronous counter differs from asynchronous counter in that:
Answer: B
Synchronous counters apply clock to all flip-flops simultaneously, eliminating propagation delay limitations of asynchronous counters
Q.11Medium
In a 4-bit ripple counter, the maximum frequency that can be counted is limited by the:
Answer: A
In ripple counters, each flip-flop must settle before the next one can toggle. The maximum countable frequency is limited by the total propagation delay through all stages.
Q.12Medium
A 3-to-8 decoder with active-low outputs has how many output lines at logic 0 when the input is 101?
Answer: C
A 3-to-8 decoder with active-low outputs means all lines are 1 except the selected one. Input 101 (5 in decimal) selects line 5, so 7 lines remain at 0.
Q.13Medium
In a Priority encoder, when multiple inputs are high simultaneously, which input gets priority?
Answer: C
Priority encoders can be designed with either highest or lowest priority encoding based on the application requirements specified in the design.
Q.14Medium
A synchronous BCD counter counts from 0000 to 1001, then resets to 0000. This requires modification of a standard 4-bit counter using:
Answer: B
BCD counters use AND gates to detect when the count reaches 1010 (10 in decimal), triggering a reset to 0000 to maintain BCD counting.
Q.15Medium
Which Boolean algebra theorem states that A + A·B = A?
Answer: A
The Absorption theorem simplifies expressions of the form A + A·B to just A, eliminating redundant terms.
Q.16Medium
The propagation delay in a synchronous counter is:
Answer: A
In synchronous counters, all flip-flops receive the same clock pulse simultaneously, so propagation delay equals one flip-flop delay, not cumulative.
Q.17Medium
In Quine-McCluskey method, prime implicants are:
Answer: B
Prime implicants are maximal groups of 1's that cannot be combined with other groups, representing the simplest possible terms.
Q.18Medium
The hold time specification for a flip-flop ensures that:
Answer: A
Hold time is the minimum duration data must remain stable after the clock edge to ensure reliable capture and operation.
Q.19Medium
In a 8-bit parallel-in serial-out (PISO) shift register, how many clock pulses are needed to output all data?
Answer: B
To shift out 8 bits of data serially, 8 clock pulses are required, one for each bit output.
Q.20Medium
Which characteristic distinguishes CMOS gates from TTL gates in practical applications?
Answer: C
CMOS gates consume minimal static power (only during transitions), making them ideal for battery-operated and portable applications.
