The thermal runaway condition in a BJT occurs because:
Answer: A
Thermal runaway is a positive feedback mechanism: temperature ↑ → V_BE ↓ (≈ -2mV/°C) → I_B ↑ → I_C ↑ → P_dissipated ↑ → T ↑, creating instability. β also increases with temperature.
Q.22Hard
The charge storage time in a BJT switch is primarily due to:
Answer: C
Storage time (t_s) occurs because excess minority carriers accumulate in the base during saturation. When the input is removed, these carriers must recombine or diffuse out before reverse current can flow, causing delay in switching off.
Q.23Hard
In a PIN diode used as an RF switch, the operating principle is based on:
Answer: C
PIN diodes have wide intrinsic regions. When forward biased, high carrier concentration (conductivity modulation) is established in the I-region, giving low impedance. When reverse biased, carriers are swept out, giving high impedance—ideal for RF switching.
Q.24Hard
The noise figure of an amplifier is defined as:
Answer: C
Noise Figure F = (SNR_in)/(SNR_out) = (input noise power × gain)/(output noise power). It represents the degradation in SNR due to the amplifier's internal noise contributions.
Q.25Hard
The substrate effect in a MOSFET causes:
Answer: D
Body bias effect: reverse substrate bias increases depletion width, increasing V_T (back-gate bias effect). This reduces g_m and changes I_D characteristics. The effect follows V_T = V_T0 + γ(√(2φ_F + V_SB) - √(2φ_F)).
Advertisement
Q.26Hard
The frequency response of a BJT amplifier is limited at high frequencies primarily by:
Answer: B
The base-collector capacitance C_bc exhibits the Miller effect, appearing as (1+|A_v|)C_bc at the base, creating a dominant pole that limits bandwidth. This is the primary high-frequency limitation in BJT amplifiers, with f_T ≈ g_m/(2π(C_bc(1+A_v) + C_be)).
Q.27Hard
A tunnel diode exhibits negative differential resistance. At what operating point is the dynamic resistance most negative?
Answer: C
Negative differential resistance occurs in the region between peak and valley current (Ip to Iv), where current decreases with increasing voltage.
Q.28Hard
A CMOS logic gate has static power dissipation. Which phenomenon is primarily responsible for this in 2024 technology nodes?
Answer: A
In modern sub-28nm nodes, static power dominates due to increased leakage from subthreshold conduction (IOFF) and gate-induced drain leakage (GIDL).
Q.29Hard
A MESFET (Metal-Semiconductor FET) differs from a JFET primarily in which aspect?
Answer: A
MESFET uses Schottky (metal-semiconductor) junction for gate control instead of p-n junction, enabling high-frequency GaAs implementation.
Q.30Hard
In a heterostructure bipolar transistor (HBT), the wide bandgap material in the emitter provides which advantage?
Answer: A
Wide bandgap emitter (e.g., AlGaAs) blocks minority carrier injection from base, improving γE and allowing lower base doping for higher β.
Q.31Hard
For a 3-bit Johnson counter, the maximum count is:
Answer: B
Johnson counter (twisted ring counter) has 2n states for n flip-flops. For 3-bit: 2×3 = 6 states. It's more efficient than ripple counter but less than binary counter.
Q.32Hard
Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?
Answer: C
Up/Down counters require multiplexers to select between up and down count logic. Additional XOR/XNOR gates are needed to conditionally modify JK inputs based on control signal C
Q.33Hard
In Hamming code for single error correction, if the total number of data bits is 16, how many parity bits are required?
Answer: C
For Hamming code, if 'p' is the number of parity bits, then 2^p ≥ (p + data bits). For 16 data bits: 2^p ≥ p + 16. Testing: 2^5 = 32 ≥ 5 + 16 = 21. ✓
Q.34Hard
A SRAM cell requires how many transistors for a 1-bit storage?
Answer: C
A typical SRAM cell uses 6 transistors: 4 for the cross-coupled latch (2 NMOS + 2 PMOS) and 2 access transistors for read/write operations.
Q.35Hard
In pipelined architecture, what does increasing the number of pipeline stages primarily result in?
Answer: B
More pipeline stages increase throughput (instructions per cycle) but increase latency (clock-to-output delay) due to increased stage delays.
Q.36Hard
How does the Kogge-Stone adder compare to the Ripple Carry Adder in terms of propagation delay for a 32-bit addition?
Answer: B
Kogge-Stone is a parallel prefix adder with O(log n) delay compared to Ripple Carry Adder's O(n) linear delay, making it faster for larger bit widths.
Q.37Hard
In a complex digital system, what does 'Setup time' refer to?
Answer: B
Setup time is the minimum duration that the input data must be stable and valid before the active clock edge arrives at the flip-flop.
Q.38Hard
A Moore FSM differs from a Mealy FSM in which aspect?
Answer: B
Moore FSM outputs depend only on current state, while Mealy FSM outputs depend on both current state and current inputs, allowing faster response.
Q.39Hard
What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?
Answer: A
Maximum frequency = 1 / (propagation delay) = 501 ns = 1 / (50 × 10^-9 s) = 20 MHz.
Q.40Hard
In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?
Answer: C
Ideal speedup in pipelining equals the number of pipeline stages. With 5 stages and optimal conditions, speedup is approximately 5x.
