Electrical Engg (EEE)

In a priority encoder with MSB having highest priority, when I7=1 (highest priority input), the output represents position 7, which is 111 in 3-bit binary. Lower priority inputs I5 and I3 are ignored.

Setup time is a manufacturer-specified parameter that varies by IC type and technology. At 100 MHz (10 ns period), typical setup times range from 2-5 ns, but exact requirements must be verified from the datasheet. General frequency calculation alone cannot determine setup time.

Mealy machines produce outputs based on both the current state and input variables, unlike Moore machines which depend only on the current state. This makes Mealy machines more efficient in detecting sequences.

A 3-to-8 decoder requires 8 output lines. Each output is active for one unique combination of 3 inputs, requiring 8 AND gates, each with 3 inputs (one for each input variable or its complement).

Both static hazards (output glitches) and dynamic hazards (multiple transitions) can occur in combinational logic of counter design. Proper K-map grouping and implementation techniques are needed to minimize them.

For n input variables, truth table rows = 2^n. For 6 inputs: 2^6 = 64 rows.

Maximum frequency = 1/(4 × propagation delay) = 1/(4 × 10 ns) = 12.5 MHz. For ripple counters, the total delay is n × tpd.

Tristate logic provides high, low, and high-impedance states, enabling multiple devices to connect to a single bus by controlling which device actively drives the line.

Nyquist theorem states fs ≥ 2×fmax to avoid aliasing. Sampling below this rate causes frequency components to fold back and corrupt the signal.

Combinational circuits produce outputs based solely on current inputs. Sequential circuits have memory elements (flip-flops) and outputs depend on input history.