For a 3-bit Johnson counter, the maximum count is:
Answer: B
Johnson counter (twisted ring counter) has 2n states for n flip-flops. For 3-bit: 2×3 = 6 states. It's more efficient than ripple counter but less than binary counter.
Q.2Hard
Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?
Answer: C
Up/Down counters require multiplexers to select between up and down count logic. Additional XOR/XNOR gates are needed to conditionally modify JK inputs based on control signal C
Q.3Hard
In Hamming code for single error correction, if the total number of data bits is 16, how many parity bits are required?
Answer: C
For Hamming code, if 'p' is the number of parity bits, then 2^p ≥ (p + data bits). For 16 data bits: 2^p ≥ p + 16. Testing: 2^5 = 32 ≥ 5 + 16 = 21. ✓
Q.4Hard
A SRAM cell requires how many transistors for a 1-bit storage?
Answer: C
A typical SRAM cell uses 6 transistors: 4 for the cross-coupled latch (2 NMOS + 2 PMOS) and 2 access transistors for read/write operations.
Q.5Hard
In pipelined architecture, what does increasing the number of pipeline stages primarily result in?
Answer: B
More pipeline stages increase throughput (instructions per cycle) but increase latency (clock-to-output delay) due to increased stage delays.
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Q.6Hard
How does the Kogge-Stone adder compare to the Ripple Carry Adder in terms of propagation delay for a 32-bit addition?
Answer: B
Kogge-Stone is a parallel prefix adder with O(log n) delay compared to Ripple Carry Adder's O(n) linear delay, making it faster for larger bit widths.
Q.7Hard
In a complex digital system, what does 'Setup time' refer to?
Answer: B
Setup time is the minimum duration that the input data must be stable and valid before the active clock edge arrives at the flip-flop.
Q.8Hard
A Moore FSM differs from a Mealy FSM in which aspect?
Answer: B
Moore FSM outputs depend only on current state, while Mealy FSM outputs depend on both current state and current inputs, allowing faster response.
Q.9Hard
What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?
Answer: A
Maximum frequency = 1 / (propagation delay) = 501 ns = 1 / (50 × 10^-9 s) = 20 MHz.
Q.10Hard
In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?
Answer: C
Ideal speedup in pipelining equals the number of pipeline stages. With 5 stages and optimal conditions, speedup is approximately 5x.
Q.11Hard
A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?
Answer: C
Using K-map for three variables: (A'BC) + (AB'C) + (ABC') = C(A'B + AB') + ABC' = C(A ⊕ B) + ABC'. This represents XOR operation with an additional term, which is the minimal form requiring fewer gates than other options.
