Electronics (ECE) - MCQ Practice Questions

For n-channel depletion MOSFET, when VGS = 0 V (which is greater than Vto = -3 V), the channel is open and device conducts. With VGS > Vto and positive VDS, the device operates in saturation. Depletion-mode devices conduct at VGS = 0.

XOR gate has 2 ones in output (when inputs are different). OR has 3 ones. AND has 1 one. These are odd. XNOR has 2 ones (even). XOR is most commonly cited.

A combinational circuit can be completely defined using truth table, Boolean expressions, or logic diagram. All three are equivalent representations.

Using Boolean algebra: A + AB + ABC = A(1 + B + BC) = A(1) = A. The dominant term A absorbs all other terms.

Hamming distance = number of positions where bits differ. 1011101 vs 1001001: positions 3, 5, 6 differ. Hamming distance = 3.

Majority function outputs 1 when majority (2 or more) inputs are 1. Expression: AB + BC + AC covers all cases where at least 2 inputs are 1.

In a 4-bit binary counter, states cycle from 0000 to 1111 (0 to 15). After 1111, it wraps around to 0000 (overflow occurs).

A 4-variable K-map has 2^4 = 16 cells, each representing one minterm. To cover all minterms, minimum 16 cells are needed.

In synchronous counters, all flip-flops change simultaneously, so maximum frequency is determined by one flip-flop delay. f_max = 1/t_pd = $\frac{1}{10}$ns = 100 MHz.

An n-bit counter has 2^n possible states (from 0 to 2^n - 1). For 3-bit counter: states are 0 to 7 (000 to 111).

Mealy machine output depends on both present state and present input. Moore machine output depends only on present state. Mealy machines are more efficient.

Synchronous counters clock all flip-flops simultaneously, eliminating propagation delay problems. This allows higher operating frequencies without cumulative timing errors present in ripple counters

Booth's algorithm replaces consecutive 1s with a single subtraction and addition operation. Consecutive 1s (like 0111) are treated as 1000-1, reducing computation steps compared to processing each 1 individually

Setup time (tsu) is the minimum duration the input signal must remain stable and valid before the active clock edge for reliable capture and state change

For modulo-N counter, minimum flip-flops required = ⌈log₂(N)⌉. For modulo-6: ⌈log₂(6)⌉ = ⌈2.58⌉ = 3 flip-flops (counts 0-5)

An n-variable Boolean function can be efficiently implemented using a 2ⁿ-to-1 multiplexer where variables form select lines and minterms form data inputs, achieving minimal gate implementation

2's complement subtraction (A-B) converts to addition A+2's complement of B. This requires 4 full adders (for addition) and XOR gates (for bit complementing), avoiding dedicated subtractors

A magnitude comparator produces exactly 3 mutually exclusive outputs: A>B (1,0,0) or A=B (0,1,0) or A<B (0,0,1). These are the only 3 possible comparison results for any input pair

Hold time (th) is the minimum duration input must remain stable after the clock edge. Violation can cause metastability—a state where flip-flop output is uncertain or oscillates unpredictably

Two cascaded 4-bit counters form an 8-bit counter system. Maximum count = 2⁸ - 1 = 255 (counts from 0 to 255, total 256 states)