Electronics (ECE) - MCQ Practice Questions

De Morgan's Law states (AB)' = A' + B' and (A+B)' = A'B'. Option C correctly represents one form of this law.

Ripple counters have cascading propagation delays as each stage must wait for the previous stage to settle, making them slower than synchronous counters.

A 4:2 encoder has 4 inputs and 2 outputs. However, for 8 inputs, a 3:8 encoder or 8:3 decoder is needed. Input line 5 would give binary 101.

A Schmitt trigger converts analog input to digital output with hysteresis, providing noise immunity and cleaner transitions.

Sum-of-Products form involves taking the AND (product) of variables and then OR (sum) of all such products to form the logic function.

Fanout is the maximum number of gate inputs of the same type that one gate output can reliably drive without degradation.

A D latch is transparent (passes input to output) when the Enable/Control signal is HIGH, and latches the value when it goes LOW.

In a 4-bit ripple counter, the output frequency of the last stage is f_clock / 2^4 = 16 MHz / 16 = 1 MHz.

Asynchronous reset directly resets the flip-flop without waiting for a clock pulse, providing immediate action regardless of clock state.

In a 4-bit synchronous counter, the MSB output toggles every 2^4 = 16 clock cycles. Therefore, MSB frequency = 10 MHz / 16 = 625 kHz. This is the divide-by-16 behavior of a 4-bit counter.