Electronics and Communication questions reward anyone who is comfortable moving between the time domain and the frequency domain. This set covers network theory, analog and digital circuits, signals and systems, control systems, communication systems, and electromagnetics. Numerical solutions keep the units visible at every step, since a dropped factor is the most common reason a correct method still produces a wrong option.
Which encoding scheme minimizes errors during binary-to-decimal conversion in digital systems?
Answer: B
Gray Code changes only one bit between consecutive numbers, minimizing transition errors. This prevents multiple simultaneous bit transitions that could cause undefined intermediate states
Q.62Medium
In a state machine with 7 states, how many flip-flops are needed for the state register?
Answer: B
For N states, minimum flip-flops required = ⌈log₂(N)⌉. For 7 states: ⌈log₂(7)⌉ = ⌈2.807⌉ = 3 flip-flops (can represent 2³=8 states)
Q.63Medium
In a synchronous counter with n flip-flops, what is the maximum frequency at which the counter can operate?
Answer: B
In synchronous counters, all flip-flops are clocked simultaneously, so the maximum frequency is limited only by the propagation delay of a single flip-flop, not the cumulative delay.
Q.64Medium
In a Johnson counter with 4 flip-flops, what is the maximum count sequence length?
Answer: B
A Johnson counter (twisted ring counter) has a sequence length of 2n, where n is the number of flip-flops. For 4 flip-flops: 2×4 = 8 states.
Q.65Medium
Which logic gate is used in a full adder to generate the carry output?
Answer: C
The carry output of a full adder is: C_out = (A·B) + (B·C_in) + (A·C_in), which requires both AND and OR gates.
Q.66Medium
What is the setup time of a flip-flop?
Answer: B
Setup time (t_su) is the minimum duration that the input signal must be stable and valid before the active clock edge for reliable operation.
Q.67Medium
In a 3-to-8 decoder, if the enable pin is active low and all select lines are 0, what will be the output?
Answer: C
In a 3-to-8 decoder with active low enable and select lines = 000, only output 0 is activated (becomes 0), while all others remain 1.
Q.68Medium
In Gray code, how many bits change when transitioning from 5 (0101) to 6 (0110)?
Answer: A
Gray code for 5 is 0111 and for 6 is 0101. Only 1 bit changes between consecutive numbers, which is the main advantage of Gray code.
Q.69Medium
A 32×8 ROM has how many address lines and data lines respectively?
Answer: A
For 32 memory locations, we need log2(32) = 5 address lines. The data width is 8 bits, hence 8 data lines.
Q.70Medium
A 4-bit Ripple Carry Adder has a total propagation delay of 12 ns. If each full adder stage has a propagation delay of 3 ns, what is the delay for carry propagation?
Answer: B
In a 4-bit ripple carry adder, the carry must propagate through 3 stages (from FA1 to FA4), giving delay = 3 × 3 ns = 9 ns.
Q.71Medium
What is the main advantage of a Carry Lookahead Adder (CLA) over a Ripple Carry Adder (RCA)?
Answer: B
CLA reduces propagation delay from O(n) to O(log n) by calculating carry signals in parallel, making it much faster than RCA.
Q.72Medium
What is the maximum frequency of operation for a JK flip-flop with setup time 5ns, hold time 3ns, and propagation delay 8ns?
Answer: C
Maximum frequency = 1/(setup time + propagation delay) = 1/(5+3)ns = 81ns = 125 MHz.
Q.73Medium
In a Mealy state machine, the output depends on which of the following?
Answer: B
Mealy machines have outputs dependent on both current state and current input, unlike Moore machines which depend only on state.
Q.74Medium
In a 4-bit Binary Weighted DAC, what is the weight of the MSB compared to the LSB?
Answer: C
For a 4-bit DAC, MSB weight = 2^(4-1) = 8 times the LSB weight.
Q.75Medium
In Booth's algorithm for multiplication, what is the purpose of examining the last two bits (current and previous)?
Answer: A
Booth's algorithm examines consecutive bits to reduce the number of addition operations by detecting transitions from 0 to 1 and 1 to 0.
Q.76Medium
How many AND gates are required to implement a 3:8 decoder?
Answer: C
A 3:8 decoder has 8 output lines, and each requires one AND gate (with appropriate inversions of inputs).
Q.77Medium
In a synchronous counter design, what is the main advantage over an asynchronous counter?
Answer: B
Synchronous counters have all flip-flops clocked simultaneously, eliminating propagation delay issues and glitches present in asynchronous counters.
Q.78Medium
Which of the following represents the canonical form of the Boolean expression for XOR gate?
Answer: D
XOR truth table: Y=1 when inputs differ. Both AB' + A'B and A'B + AB' are equivalent canonical forms.
Q.79Medium
In a Finite State Machine (FSM) with 7 states, what is the minimum number of flip-flops required?
