Electronics (ECE) - MCQ Practice Questions

Gray Code changes only one bit between consecutive numbers, minimizing transition errors. This prevents multiple simultaneous bit transitions that could cause undefined intermediate states

For N states, minimum flip-flops required = ⌈log₂(N)⌉. For 7 states: ⌈log₂(7)⌉ = ⌈2.807⌉ = 3 flip-flops (can represent 2³=8 states)

In synchronous counters, all flip-flops are clocked simultaneously, so the maximum frequency is limited only by the propagation delay of a single flip-flop, not the cumulative delay.

A Johnson counter (twisted ring counter) has a sequence length of 2n, where n is the number of flip-flops. For 4 flip-flops: 2×4 = 8 states.

The carry output of a full adder is: C_out = (A·B) + (B·C_in) + (A·C_in), which requires both AND and OR gates.

Setup time (t_su) is the minimum duration that the input signal must be stable and valid before the active clock edge for reliable operation.

In a 3-to-8 decoder with active low enable and select lines = 000, only output 0 is activated (becomes 0), while all others remain 1.

Gray code for 5 is 0111 and for 6 is 0101. Only 1 bit changes between consecutive numbers, which is the main advantage of Gray code.

For 32 memory locations, we need log2(32) = 5 address lines. The data width is 8 bits, hence 8 data lines.

In a 4-bit ripple carry adder, the carry must propagate through 3 stages (from FA1 to FA4), giving delay = 3 × 3 ns = 9 ns.

CLA reduces propagation delay from O(n) to O(log n) by calculating carry signals in parallel, making it much faster than RCA.

Maximum frequency = 1/(setup time + propagation delay) = 1/(5+3)ns = $\frac{1}{8}$ns = 125 MHz.

Mealy machines have outputs dependent on both current state and current input, unlike Moore machines which depend only on state.

For a 4-bit DAC, MSB weight = 2^(4-1) = 8 times the LSB weight.

Booth's algorithm examines consecutive bits to reduce the number of addition operations by detecting transitions from 0 to 1 and 1 to 0.

A 3:8 decoder has 8 output lines, and each requires one AND gate (with appropriate inversions of inputs).

Synchronous counters have all flip-flops clocked simultaneously, eliminating propagation delay issues and glitches present in asynchronous counters.

XOR truth table: Y=1 when inputs differ. Both AB' + A'B and A'B + AB' are equivalent canonical forms.

Minimum flip-flops needed = ⌈log₂(number of states)⌉ = ⌈log₂(7)⌉ = 3.

A Priority Encoder produces a binary output representing the highest priority active input among multiple inputs.