Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
What is the primary advantage of CMOS logic over TTL logic in modern designs?
Answer: B
CMOS logic offers significantly lower power consumption (only during switching) and better noise margins compared to TTL, making it ideal for modern low-power applications.
Q.182Easy
In a multiplexer with 8 input lines, how many output lines are present?
Answer: A
A multiplexer, regardless of the number of inputs, has only one output line. The select lines determine which input is routed to that output.
Q.183Easy
De Morgan's theorem states that (A·B)' equals:
Answer: A
De Morgan's first theorem states (A·B)' = A' + B'. The complement of AND equals OR of complements.
Q.184Easy
A 4-bit binary counter requires how many flip-flops to count from 0 to 15?
Answer: B
A 4-bit counter can represent 2^4 = 16 states (0 to 15), requiring exactly 4 flip-flops.
Q.185Easy
Which logic gate produces a HIGH output only when all inputs are HIGH?
Answer: B
AND gate outputs HIGH only when all inputs are HIGH. This is its fundamental definition.
Q.186Easy
What is the minimum number of NAND gates required to implement a NOT gate?
Answer: A
A single NAND gate with both inputs tied together acts as a NOT gate (inverter).
Q.187Easy
In a J-K flip-flop, when J=1 and K=1, the output will:
Answer: B
When J=1 and K=1, the J-K flip-flop toggles its state on each clock pulse.
Q.188Easy
A 3-to-8 decoder has how many output lines?
Answer: C
A 3-to-8 decoder has 3 input lines and 2^3 = 8 output lines, one for each possible input combination.
Q.189Easy
Which of the following is the correct relationship for setup time in sequential circuits?
Answer: B
Setup time is the minimum duration that input data must remain stable before the active clock edge for proper capture by the flip-flop.
Q.190Easy
A Karnaugh map with 5 variables requires a minimum of how many cells?
Answer: B
A 5-variable K-map requires 2^5 = 32 cells, typically arranged as two 4x4 grids representing the fifth variable's 0 and 1 states.
Q.191Easy
In a multiplexer circuit, if there are 16 output lines, how many select lines are required?
Answer: B
For n select lines, 2^n output lines are possible. Here 2^4 = 16, so 4 select lines are needed. This is a standard 16:1 multiplexer.
Q.192Easy
In a BCD (Binary Coded Decimal) counter, what is the maximum count value?
Answer: A
BCD represents decimal digits 0-9 using 4 bits. A single BCD counter counts from 0 to 9, after which it resets.
Q.193Easy
Which semiconductor technology provides the lowest static power consumption?
Answer: B
CMOS has virtually zero static power consumption because complementary transistors prevent direct paths from supply to ground in steady state.
Q.194Easy
A combinational circuit has 6 input variables. The minimum number of rows required in its truth table is:
Answer: B
For n input variables, truth table rows = 2^n. For 6 inputs: 2^6 = 64 rows.
Q.195Easy
A 3-to-8 decoder is used in a digital system. How many AND gates with minimum inputs are required?
Answer: B
A 3-to-8 decoder requires 8 output lines. Each output is active for one unique combination of 3 inputs, requiring 8 AND gates, each with 3 inputs (one for each input variable or its complement).
