Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
In a Priority encoder, when multiple inputs are high simultaneously, which input gets priority?
Answer: C
Priority encoders can be designed with either highest or lowest priority encoding based on the application requirements specified in the design.
Q.282Medium
A synchronous BCD counter counts from 0000 to 1001, then resets to 0000. This requires modification of a standard 4-bit counter using:
Answer: B
BCD counters use AND gates to detect when the count reaches 1010 (10 in decimal), triggering a reset to 0000 to maintain BCD counting.
Q.283Medium
Which Boolean algebra theorem states that A + A·B = A?
Answer: A
The Absorption theorem simplifies expressions of the form A + A·B to just A, eliminating redundant terms.
Q.284Medium
The propagation delay in a synchronous counter is:
Answer: A
In synchronous counters, all flip-flops receive the same clock pulse simultaneously, so propagation delay equals one flip-flop delay, not cumulative.
Q.285Medium
In Quine-McCluskey method, prime implicants are:
Answer: B
Prime implicants are maximal groups of 1's that cannot be combined with other groups, representing the simplest possible terms.
Q.286Medium
The hold time specification for a flip-flop ensures that:
Answer: A
Hold time is the minimum duration data must remain stable after the clock edge to ensure reliable capture and operation.
Q.287Medium
In a 8-bit parallel-in serial-out (PISO) shift register, how many clock pulses are needed to output all data?
Answer: B
To shift out 8 bits of data serially, 8 clock pulses are required, one for each bit output.
Q.288Medium
Which characteristic distinguishes CMOS gates from TTL gates in practical applications?
Answer: C
CMOS gates consume minimal static power (only during transitions), making them ideal for battery-operated and portable applications.
Q.289Medium
In a D flip-flop, the output Q follows the input D on the occurrence of which signal?
Answer: B
A D flip-flop captures the input data on the rising edge of the clock pulse and transfers it to the output Q.
Q.290Medium
Which type of ADC provides the fastest conversion?
Answer: C
Flash ADC uses parallel comparators and provides the fastest conversion as it converts in a single clock pulse, though at higher cost and power consumption.
Q.291Medium
What is the output frequency of a decade counter (MOD-10 counter) when input frequency is 1 MHz?
Answer: A
A decade counter divides the input frequency by 10. Output frequency = 1 MHz ÷ 10 = 100 kHz.
Q.292Medium
The setup time of a flip-flop is defined as the minimum time during which the input must be stable:
Answer: A
Setup time is the minimum time before the active clock edge during which the input data must remain stable to ensure correct capture.
Q.293Medium
Which of the following logic families has the highest power dissipation?
Answer: B
ECL (Emitter Coupled Logic) has the highest power dissipation among standard logic families but offers excellent speed performance.
Q.294Medium
A 16:1 multiplexer requires how many select lines to uniquely identify each input?
Answer: B
For 16 inputs, select lines required = log₂(16) = 4. These 4 lines can produce 2⁴ = 16 unique combinations.
Q.295Medium
In asynchronous (ripple) counters, the propagation delay issue leads to:
Answer: A
In ripple counters, each flip-flop triggers the next, causing cumulative delay. Total delay = n × tₚ, limiting maximum frequency.
Q.296Medium
Which digital circuit is used to convert parallel data into serial form?
Answer: C
A Parallel-In-Serial-Out (PISO) shift register accepts parallel data and outputs it serially, bit by bit.
Q.297Medium
The Boolean expression A·B + A·B' can be simplified to:
Answer: A
A·B + A·B' = A(B + B') = A·1 = A (using factoring and complement law)
Q.298Medium
What is the hold time of a flip-flop?
Answer: A
Hold time is the minimum duration data input must remain stable after the active clock edge.
Q.299Medium
A 32:1 multiplexer can be constructed using how many 4:1 multiplexers?
Answer: B
A 32:1 MUX requires 8 4:1 MUXes in first stage (432=8) and 2 4:1 MUXes in second stage, totaling 10. However, using 6 4:1 MUXes is an efficient hierarchical implementation with proper decoding.
Q.300Medium
Which of the following flip-flops is most suitable for frequency division applications?
Answer: B
T (toggle) flip-flop is ideal for frequency division as it divides input frequency by 2 when toggling.
