Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
Which of the following is a characteristic of combinational circuits?
Answer: B
Combinational circuits have outputs that depend solely on the current input values, with no memory or feedback elements involved.
Q.22Hard
A full adder can be implemented using how many NAND gates minimum?
Answer: C
A full adder requires 9 NAND gates minimum when implemented using NAND gates exclusively to realize the sum and carry outputs.
Q.23Easy
In the 2024-25 examination pattern, which logic family provides the lowest power consumption?
Answer: C
CMOS (Complementary Metal-Oxide-Semiconductor) logic has the lowest power consumption, making it the preferred choice for modern digital systems and portable devices.
Q.24Medium
A 3-to-8 decoder with active-low outputs has how many output lines at logic 0 when the input is 101?
Answer: C
A 3-to-8 decoder with active-low outputs means all lines are 1 except the selected one. Input 101 (5 in decimal) selects line 5, so 7 lines remain at 0.
Q.25Medium
In a Priority encoder, when multiple inputs are high simultaneously, which input gets priority?
Answer: C
Priority encoders can be designed with either highest or lowest priority encoding based on the application requirements specified in the design.
Q.26Easy
The setup time of a flip-flop is defined as:
Answer: B
Setup time is the minimum duration the input data must remain stable and valid before the active clock edge for reliable operation.
Q.27Easy
In a Karnaugh map, what does a larger group of adjacent 1's represent?
Answer: B
Larger groups in K-maps represent simplification with fewer variables in the resulting Boolean expression, reducing circuit complexity.
Q.28Medium
A synchronous BCD counter counts from 0000 to 1001, then resets to 0000. This requires modification of a standard 4-bit counter using:
Answer: B
BCD counters use AND gates to detect when the count reaches 1010 (10 in decimal), triggering a reset to 0000 to maintain BCD counting.
Q.29Medium
Which Boolean algebra theorem states that A + A·B = A?
Answer: A
The Absorption theorem simplifies expressions of the form A + A·B to just A, eliminating redundant terms.
Q.30Easy
In a multiplexer, the number of select lines required to select from 16 data inputs is:
Answer: B
For 2^n data inputs, n select lines are needed. 2^4 = 16, so 4 select lines are required for a 16-to-1 multiplexer.
Q.31Medium
The propagation delay in a synchronous counter is:
Answer: A
In synchronous counters, all flip-flops receive the same clock pulse simultaneously, so propagation delay equals one flip-flop delay, not cumulative.
Q.32Easy
Which of the following is used to convert analog signals to digital for processing?
Answer: C
ADCs are specifically designed to convert continuous analog signals into discrete digital representations for digital processing systems.
Q.33Medium
In Quine-McCluskey method, prime implicants are:
Answer: B
Prime implicants are maximal groups of 1's that cannot be combined with other groups, representing the simplest possible terms.
Q.34Easy
A JK flip-flop with J=1, K=1 and clock pulse will:
Answer: C
When both J and K inputs are 1 in a JK flip-flop, the output toggles on the clock pulse, changing from 0 to 1 or 1 to 0.
Q.35Medium
The hold time specification for a flip-flop ensures that:
Answer: A
Hold time is the minimum duration data must remain stable after the clock edge to ensure reliable capture and operation.
Q.36Medium
In a 8-bit parallel-in serial-out (PISO) shift register, how many clock pulses are needed to output all data?
Answer: B
To shift out 8 bits of data serially, 8 clock pulses are required, one for each bit output.
Q.37Medium
Which characteristic distinguishes CMOS gates from TTL gates in practical applications?
Answer: C
CMOS gates consume minimal static power (only during transitions), making them ideal for battery-operated and portable applications.
Q.38Hard
In a Gray code counter, consecutive counts differ by exactly:
Answer: A
Gray code is designed such that consecutive values differ in exactly one bit position, reducing transition errors in digital systems.
Q.39Easy
In a 4-to-1 multiplexer, how many select lines are required?
Answer: B
For a 4-to-1 multiplexer, we need log₂(4) = 2 select lines to choose one of 4 input lines.
Q.40Easy
What is the output of an SR flip-flop when S=1 and R=1 (NOR gate implementation)?
Answer: C
When both S=1 and R=1 in NOR-based SR flip-flop, both outputs become 0, which violates the Q and Q' complementary property, making it an invalid state.
