Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
Which Boolean theorem states that A + 0 = A and A · 1 = A?
Answer: B
The Identity law in Boolean algebra states that any variable combined with identity element (0 for OR, 1 for AND) remains unchanged.
Q.42Easy
In a ripple counter with 4 flip-flops, what is the maximum count?
Answer: B
A 4-bit counter can count from 0 to 2⁴-1 = 15 (binary: 0000 to 1111), giving a maximum count of 15.
Q.43Easy
What is the primary advantage of CMOS logic over TTL logic in modern designs?
Answer: B
CMOS logic offers significantly lower power consumption (only during switching) and better noise margins compared to TTL, making it ideal for modern low-power applications.
Q.44Medium
In a D flip-flop, the output Q follows the input D on the occurrence of which signal?
Answer: B
A D flip-flop captures the input data on the rising edge of the clock pulse and transfers it to the output Q.
Q.45Medium
Which type of ADC provides the fastest conversion?
Answer: C
Flash ADC uses parallel comparators and provides the fastest conversion as it converts in a single clock pulse, though at higher cost and power consumption.
Q.46Medium
What is the output frequency of a decade counter (MOD-10 counter) when input frequency is 1 MHz?
Answer: A
A decade counter divides the input frequency by 10. Output frequency = 1 MHz ÷ 10 = 100 kHz.
Q.47Easy
In a multiplexer with 8 input lines, how many output lines are present?
Answer: A
A multiplexer, regardless of the number of inputs, has only one output line. The select lines determine which input is routed to that output.
Q.48Medium
The setup time of a flip-flop is defined as the minimum time during which the input must be stable:
Answer: A
Setup time is the minimum time before the active clock edge during which the input data must remain stable to ensure correct capture.
Q.49Medium
Which of the following logic families has the highest power dissipation?
Answer: B
ECL (Emitter Coupled Logic) has the highest power dissipation among standard logic families but offers excellent speed performance.
Q.50Easy
De Morgan's theorem states that (A·B)' equals:
Answer: A
De Morgan's first theorem states (A·B)' = A' + B'. The complement of AND equals OR of complements.
Q.51Medium
A 16:1 multiplexer requires how many select lines to uniquely identify each input?
Answer: B
For 16 inputs, select lines required = log₂(16) = 4. These 4 lines can produce 2⁴ = 16 unique combinations.
Q.52Medium
In asynchronous (ripple) counters, the propagation delay issue leads to:
Answer: A
In ripple counters, each flip-flop triggers the next, causing cumulative delay. Total delay = n × tₚ, limiting maximum frequency.
Q.53Medium
Which digital circuit is used to convert parallel data into serial form?
Answer: C
A Parallel-In-Serial-Out (PISO) shift register accepts parallel data and outputs it serially, bit by bit.
Q.54Medium
The Boolean expression A·B + A·B' can be simplified to:
Answer: A
A·B + A·B' = A(B + B') = A·1 = A (using factoring and complement law)
Q.55Hard
In a synchronous counter design, all flip-flops receive the clock signal simultaneously. This arrangement primarily eliminates:
Answer: A
Synchronous counters eliminate propagation delay accumulation and race conditions by clocking all flip-flops simultaneously, enabling higher frequency operation.
Q.56Hard
A Schmitt trigger input is used in digital circuits primarily to:
Answer: B
Schmitt trigger provides hysteresis (different thresholds for rising/falling edges), effectively eliminating noise-induced multiple transitions on slowly changing inputs.
Q.57Hard
When implementing a 3-variable Boolean function using a 2-to-1 multiplexer instead of a 8-to-1, one variable must be:
Answer: C
A 2-to-1 MUX has only 1 select line (covering 2 input combinations). For 3 variables (8 combinations), the third variable must be processed through additional logic gates and distributed between select and data paths.
Q.58Easy
A 4-bit binary counter requires how many flip-flops to count from 0 to 15?
Answer: B
A 4-bit counter can represent 2^4 = 16 states (0 to 15), requiring exactly 4 flip-flops.
Q.59Easy
Which logic gate produces a HIGH output only when all inputs are HIGH?
Answer: B
AND gate outputs HIGH only when all inputs are HIGH. This is its fundamental definition.
Q.60Easy
What is the minimum number of NAND gates required to implement a NOT gate?
Answer: A
A single NAND gate with both inputs tied together acts as a NOT gate (inverter).
