In a J-K flip-flop, when J=1 and K=1, the output will:
Answer: B
When J=1 and K=1, the J-K flip-flop toggles its state on each clock pulse.
Q.62Medium
What is the hold time of a flip-flop?
Answer: A
Hold time is the minimum duration data input must remain stable after the active clock edge.
Q.63Medium
A 32:1 multiplexer can be constructed using how many 4:1 multiplexers?
Answer: B
A 32:1 MUX requires 8 4:1 MUXes in first stage (432=8) and 2 4:1 MUXes in second stage, totaling 10. However, using 6 4:1 MUXes is an efficient hierarchical implementation with proper decoding.
Q.64Medium
Which of the following flip-flops is most suitable for frequency division applications?
Answer: B
T (toggle) flip-flop is ideal for frequency division as it divides input frequency by 2 when toggling.
Q.65Medium
In 2's complement representation, what is the range of numbers for an 8-bit system?
Answer: A
8-bit 2's complement range is from -2^7 to 2^7-1, which is -128 to +127.
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Q.66Medium
Which characteristic of CMOS logic makes it suitable for portable devices?
Answer: B
CMOS has minimal static power consumption (only during switching), making it ideal for battery-powered devices.
Q.67Medium
How many address lines are required for a 4GB memory system?
In a priority encoder, what determines which input is encoded when multiple inputs are active?
Answer: B
Priority encoders are designed with built-in priority logic where the highest priority input (usually MSB) is encoded when multiple inputs are active.
Q.69Medium
What is the main advantage of Gray code over binary code in digital systems?
Answer: B
Gray code ensures only one bit changes between consecutive values, reducing errors in digital transitions and rotary encoders.
Q.70Easy
A 3-to-8 decoder has how many output lines?
Answer: C
A 3-to-8 decoder has 3 input lines and 2^3 = 8 output lines, one for each possible input combination.
Q.71Hard
What is the hold time constraint violation in sequential circuits?
Answer: A
Hold time violation occurs when input data changes before the hold time window after the clock edge, corrupting the captured data.
Q.72Hard
Which digital logic family provides the best balance between speed and power consumption?
Answer: B
CMOS offers optimal trade-off with low static power dissipation and moderate switching speeds suitable for most applications.
Q.73Hard
In a 4-bit BCD adder, what is the maximum sum that can be represented without requiring correction?
Answer: C
In BCD addition, a result of 18 (binary 10010) requires correction code to convert to valid BCD (1000 + carry). Sums up to 9+9=18 need correction when exceeding 9.
Q.74Hard
What is the primary function of a state machine in digital design?
Answer: B
State machines control digital circuits by transitioning through defined states based on current state, inputs, and clock signals, implementing complex logic sequences.
Q.75Hard
In a 8-bit barrel shifter, how many control bits are required to specify any shift amount?
Answer: B
For an 8-bit barrel shifter, 3 control bits can specify 2^3 = 8 different shift positions (0 to 7), covering all possible shifts.
Q.76Medium
In a synchronous counter design, what is the primary advantage over asynchronous counters?
Answer: B
Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delays that cause glitches in asynchronous designs.
Q.77Easy
Which of the following is the correct relationship for setup time in sequential circuits?
Answer: B
Setup time is the minimum duration that input data must remain stable before the active clock edge for proper capture by the flip-flop.
Q.78Easy
A Karnaugh map with 5 variables requires a minimum of how many cells?
Answer: B
A 5-variable K-map requires 2^5 = 32 cells, typically arranged as two 4x4 grids representing the fifth variable's 0 and 1 states.
Q.79Easy
In a multiplexer circuit, if there are 16 output lines, how many select lines are required?
Answer: B
For n select lines, 2^n output lines are possible. Here 2^4 = 16, so 4 select lines are needed. This is a standard 16:1 multiplexer.
Q.80Medium
Which logic family has the highest noise margin among the following?
Answer: C
CMOS logic has noise margins typically around 30-40% of supply voltage, superior to TTL (~0.4V) and ECL (~0.2V).
