In a BCD (Binary Coded Decimal) counter, what is the maximum count value?
Answer: A
BCD represents decimal digits 0-9 using 4 bits. A single BCD counter counts from 0 to 9, after which it resets.
Q.82Medium
Which of the following represents the De Morgan's law correctly?
Answer: B
De Morgan's law states: (A.B)' = A'+B' (NAND equals OR of inverted inputs) and (A+B)' = A'.B' (NOR equals AND of inverted inputs).
Q.83Medium
In an SR flip-flop, what happens when both S and R inputs are 1 simultaneously?
Answer: C
When both S=1 and R=1 in SR flip-flop, both Q and Q' become 1, violating the complementary relationship - this is the forbidden state.
Q.84Medium
A Johnson counter (twisted ring counter) with n flip-flops produces how many unique states before repeating?
Answer: B
A Johnson counter with n flip-flops generates 2n unique states (half of the theoretical 2^n), making it useful for decade counters.
Q.85Medium
In FPGA design, what does LUT (Lookup Table) primarily function as?
Answer: B
LUTs in FPGAs are programmable combinational logic blocks that can implement any logic function for inputs (typically 4-6 inputs).
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Q.86Medium
What is the Fan-out limit of a TTL gate, and what does it signify?
Answer: B
Fan-out (typically 10 for TTL) is the maximum number of logic gate inputs that an output can reliably drive while maintaining specified voltage levels.
Q.87Easy
Which semiconductor technology provides the lowest static power consumption?
Answer: B
CMOS has virtually zero static power consumption because complementary transistors prevent direct paths from supply to ground in steady state.
Q.88Hard
In a sequential logic circuit, metastability occurs when the input changes relative to the clock edge. How can this be minimized?
Answer: B
Synchronizer circuits use cascaded flip-flops to provide settling time between asynchronous signal and sampling clock, reducing metastability risk.
Q.89Medium
What is the characteristic equation of a D flip-flop?
Answer: A
The D flip-flop captures input D on clock edge and transfers it to output: Q(n+1) = D. This represents 'data' or 'delay' functionality.
Q.90Hard
In asynchronous sequential circuits, what is the primary concern regarding state transitions?
Answer: B
Asynchronous circuits lack global clock, so multiple state variables can change simultaneously, causing race conditions and hazards if not carefully designed.
Q.91Medium
Which of the following correctly describes the difference between combinational and sequential logic?
Answer: B
Combinational circuits produce outputs based solely on current inputs. Sequential circuits have memory elements (flip-flops) and outputs depend on input history.
Q.92Hard
In the context of digital signal processing, what is the Nyquist sampling theorem's requirement?
Answer: B
Nyquist theorem states fs ≥ 2×fmax to avoid aliasing. Sampling below this rate causes frequency components to fold back and corrupt the signal.
Q.93Medium
What is the main purpose of tristate logic (three-state logic) in digital circuits?
Answer: B
Tristate logic provides high, low, and high-impedance states, enabling multiple devices to connect to a single bus by controlling which device actively drives the line.
Q.94Medium
In a 4-bit binary counter using JK flip-flops, if the propagation delay of each flip-flop is 10 ns, what is the maximum counting frequency?
Answer: B
Maximum frequency = 1/(4 × propagation delay) = 1/(4 × 10 ns) = 12.5 MHz. For ripple counters, the total delay is n × tpd.
Q.95Easy
A combinational circuit has 6 input variables. The minimum number of rows required in its truth table is:
Answer: B
For n input variables, truth table rows = 2^n. For 6 inputs: 2^6 = 64 rows.
Q.96Hard
In a synchronous counter design using SR flip-flops with Karnaugh map minimization, which hazard is most critical in the implementation?
Answer: C
Both static hazards (output glitches) and dynamic hazards (multiple transitions) can occur in combinational logic of counter design. Proper K-map grouping and implementation techniques are needed to minimize them.
Q.97Easy
A 3-to-8 decoder is used in a digital system. How many AND gates with minimum inputs are required?
Answer: B
A 3-to-8 decoder requires 8 output lines. Each output is active for one unique combination of 3 inputs, requiring 8 AND gates, each with 3 inputs (one for each input variable or its complement).
Q.98Medium
In a Mealy state machine design for a sequence detector (detecting '101'), the output depends on:
Answer: C
Mealy machines produce outputs based on both the current state and input variables, unlike Moore machines which depend only on the current state. This makes Mealy machines more efficient in detecting sequences.
Q.99Hard
What is the setup time requirement for a D flip-flop in a shift register operating at 100 MHz clock frequency?
Answer: D
Setup time is a manufacturer-specified parameter that varies by IC type and technology. At 100 MHz (10 ns period), typical setup times range from 2-5 ns, but exact requirements must be verified from the datasheet. General frequency calculation alone cannot determine setup time.
Q.100Medium
A priority encoder with 8 inputs has the highest priority assigned to the MSB. If inputs I7=1, I5=1, I3=1, and all others are 0, what is the output?
Answer: A
In a priority encoder with MSB having highest priority, when I7=1 (highest priority input), the output represents position 7, which is 111 in 3-bit binary. Lower priority inputs I5 and I3 are ignored.
