Electronics (ECE) - MCQ Practice Questions

In a ripple counter, each flip-flop divides the frequency by 2. The third flip-flop output frequency = 16 MHz / 2³ = $\frac{16}{8}$ = 2 MHz

XOR (Exclusive OR) gate produces HIGH output when inputs are different (01 or 10). When inputs are same (00 or 11), output is LOW

When S=0 and R=0, the SR flip-flop holds its previous state. No change occurs because neither set nor reset is activated

Decimal 5 = Binary 0101. Gray code is obtained by: G0=B0=1, G1=B0⊕B1=0⊕1=1, G2=B1⊕B2=1⊕0=1, G3=B2⊕B3=0⊕0=0. Result: 0111

Synchronous counters clock all flip-flops simultaneously, eliminating propagation delay problems. This allows higher operating frequencies without cumulative timing errors present in ripple counters

A 3-to-8 decoder has 2³ = 8 output lines. For any valid input combination, exactly 1 output line is activated (HIGH), while others remain LOW

Booth's algorithm replaces consecutive 1s with a single subtraction and addition operation. Consecutive 1s (like 0111) are treated as 1000-1, reducing computation steps compared to processing each 1 individually

Setup time (tsu) is the minimum duration the input signal must remain stable and valid before the active clock edge for reliable capture and state change

For modulo-N counter, minimum flip-flops required = ⌈log₂(N)⌉. For modulo-6: ⌈log₂(6)⌉ = ⌈2.58⌉ = 3 flip-flops (counts 0-5)

An n-variable Boolean function can be efficiently implemented using a 2ⁿ-to-1 multiplexer where variables form select lines and minterms form data inputs, achieving minimal gate implementation

'rising_edge' detects a transition from LOW (0) to HIGH (1) on a signal, commonly used in synchronous designs to trigger actions on positive clock edges

2's complement subtraction (A-B) converts to addition A+2's complement of B. This requires 4 full adders (for addition) and XOR gates (for bit complementing), avoiding dedicated subtractors

A magnitude comparator produces exactly 3 mutually exclusive outputs: A>B (1,0,0) or A=B (0,1,0) or A<B (0,0,1). These are the only 3 possible comparison results for any input pair

Hold time (th) is the minimum duration input must remain stable after the clock edge. Violation can cause metastability—a state where flip-flop output is uncertain or oscillates unpredictably

Standard ROM is programmed during manufacturing and cannot be reprogrammed by users. PROM, EPROM, and EEPROM allow user programming, but basic ROM does not

16×4 RAM means 16 memory words (locations), each storing 4 bits of data. This requires log₂(16)=4 address lines. Total capacity = 16 words × 4 bits = 64 bits

Up/Down counters require multiplexers to select between up and down count logic. Additional XOR/XNOR gates are needed to conditionally modify JK inputs based on control signal C

Two cascaded 4-bit counters form an 8-bit counter system. Maximum count = 2⁸ - 1 = 255 (counts from 0 to 255, total 256 states)

Gray Code changes only one bit between consecutive numbers, minimizing transition errors. This prevents multiple simultaneous bit transitions that could cause undefined intermediate states

For N states, minimum flip-flops required = ⌈log₂(N)⌉. For 7 states: ⌈log₂(7)⌉ = ⌈2.807⌉ = 3 flip-flops (can represent 2³=8 states)