Electronics (ECE) - MCQ Practice Questions

Understanding:

We need to find the maximum addressable memory for a processor with a 16-bit address bus.

Formula:

where $n$ is the number of address lines.

Step 1: Substitute $n=16$

Answer:

With a 16-bit address bus, the 8085 can directly address 64 KB of memory.

Quick Tip:

Each additional address line doubles the addressable space. Memorise: $2^{10}=1\text{KB}$, $2^{20}=1\text{MB}$, so $2^{16}=2^{10}\times 2^6=64\text{KB}$.

Understanding:

We need to identify which flag of the 8085 is set when the result of an operation equals zero.

Step 1: Review the 8085 flags

The 8085 has five flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY).

Step 2: Identify the Zero Flag

The Zero Flag (Z) is set to 1 whenever the result of an arithmetic or logical operation produces a result of 0x00 in the accumulator. It is reset (cleared to 0) for any non-zero result.

Step 3: Eliminate the other options

Answer:

The Zero Flag (Z) is set when the result of an operation is zero.

Understanding:

We need to determine the bit-width of the Code Segment register in the 8086 processor.

Step 1: Architecture of 8086 segment registers

The 8086 is a 16-bit processor. It has four segment registers — CS (Code Segment), DS (Data Segment), SS (Stack Segment), and ES (Extra Segment) — each of which is 16 bits wide.

Step 2: Physical address generation

Although the segment registers are 16 bits wide, the 8086 generates a 20-bit physical address using the formula:

This allows addressing up to $2^{20}=1\text{MB}$ of memory, but the register itself stores only 16 bits.

Answer:

Each segment register in the 8086, including the CS register, is 16 bits wide.

Quick Tip:

Do not confuse the physical address width (20 bits) with the segment register size (16 bits). The 20-bit address is derived by shifting the 16-bit segment value left by 4 bits (multiplying by 16) and adding the 16-bit offset.

Understanding:

We need to trace the execution of two 8085 instructions and determine the Accumulator value and flag status.

Formula:

Step 1: Perform the addition

In hex: $\text{FA}+\text{FA}=250+250=500=\text{1F4H}$

Step 2: Determine the 8-bit result

Since the 8085 accumulator is 8 bits, only the lower 8 bits are retained:

The 9th bit (carry out) sets the Carry Flag: $\text{CY}=1$

Step 3: Check the Sign Flag

Bit 7 of $\text{F4H}=11110100_2$ is $1$, so the Sign Flag $\text{S}=1$.

Step 4: Check the Zero Flag

$\text{F4H}\ne \text{00H}$, so $\text{Z}=0$.

Answer:

After ADD A, the Accumulator holds F4H with CY = 1 and S = 1.

Quick Tip:

In 8085 addition, CY is set whenever the 8-bit sum exceeds 0xFF (255). Here $250\times 2=500>255$, so a carry is guaranteed.

Understanding:

We need to compute the 20-bit physical address from the segment and offset registers.

Formula:

Multiplying by 16 is equivalent to a 4-bit left shift (appending one hex zero).

Step 1: Shift CS left by 4 bits

Step 2: Add the Instruction Pointer

Answer:

The physical address of the next instruction is 12300H.

Quick Tip:

Always append a '0' (hex digit) to the segment register value first, then add the offset. This simple trick avoids multiplication errors in exams.

Understanding:

We need to identify the role of the ALE signal in the 8085 microprocessor.

Step 1: The multiplexed bus of the 8085

The 8085 uses a multiplexed address/data bus on pins AD0–AD7. During the first clock cycle (T1) of a machine cycle, these pins carry the lower 8 bits of the 16-bit address. During subsequent cycles, the same pins carry the 8-bit data.

Step 2: Role of ALE

ALE (Address Latch Enable) goes HIGH during T1 to indicate that the AD0–AD7 pins are currently carrying address information. An external latch (such as the 74LS373) uses this ALE pulse to capture and hold the lower 8 address bits, effectively demultiplexing the bus.

Step 3: Eliminate other options

Answer:

ALE is used to demultiplex the lower-order address bits from the multiplexed AD0–AD7 lines by latching the address during the T1 state.

Understanding:

We need to identify the stack pointer register in the 8085 and its behavior during a CALL instruction.

Step 1: The Stack Pointer in 8085

The 8085 has a dedicated 16-bit Stack Pointer (SP) register. The stack grows downward in memory (toward lower addresses).

Step 2: Operation of CALL

When CALL is executed:

1. SP is decremented by 1, and the high byte of the Program Counter (PC) is pushed.

2. SP is decremented again by 1, and the low byte of the PC is pushed.

Net effect: SP decreases by 2, and the 16-bit return address is stored on the stack.

Formula:

Step 3: Eliminate other options

HL is a general-purpose register pair, not the stack pointer. SP is always incremented (not decremented) on RET, not on CALL.

Answer:

The dedicated SP register is decremented by 2, and the return address (current PC value) is pushed onto the stack.

Quick Tip:

Remember: CALL decrements SP (stack grows down), RET increments SP (stack shrinks). This is a frequent exam trap.

Understanding:

We need to determine the number of machine cycles for the 8085 instruction LDA 2050H.

Step 1: Identify the instruction format

LDA is a 3-byte instruction: one opcode byte followed by two address bytes (low byte then high byte of the 16-bit address).

Step 2: Count machine cycles

The execution of LDA 2050H involves the following machine cycles:

1. Opcode Fetch (OF): Fetch the opcode byte from memory.

2. Memory Read (MR): Read the low-order byte of the address (50H).

3. Memory Read (MR): Read the high-order byte of the address (20H).

4. Memory Read (MR): Read the data from the address 2050H into the Accumulator.

Total machine cycles = $4$

Step 3: Count T-states for verification

LDA uses $13$ T-states: OF = 4, MR = 3, MR = 3, MR = 3 $\Rightarrow$ 4 + 3 + 3 + 3 = 13 T-states, consistent with 4 machine cycles.

Answer:

The LDA 2050H instruction requires 4 machine cycles.

Quick Tip:

For LDA/STA/LHLD/SHLD, always count 4 machine cycles: 1 opcode fetch + 2 address byte reads + 1 data operation. This is a commonly tested fact.

Understanding:

We need to identify which flag controls auto-increment or auto-decrement of SI and DI during 8086 string operations.

Step 1: 8086 String Instructions

String instructions such as MOVSB, MOVSW, LODSB, STOSB, CMPSB, and SCASB use SI (Source Index) and DI (Destination Index) registers, which are automatically updated after each operation.

Step 2: The Direction Flag (DF)

Step 3: Eliminate other options

Answer:

The Direction Flag (DF) controls whether SI and DI are incremented or decremented during string operations.

Quick Tip:

Remember CLD (Clear Direction Flag) → auto-increment (forward processing) and STD (Set Direction Flag) → auto-decrement (backward processing). This distinction is frequently tested.

Understanding:

We need to find how many $8\text{KB}$ blocks fit in the $64\text{KB}$ address space of the 8085, given that the upper 3 address bits select each block.

Formula:

Step 1: Compute using total address space and block size

Step 2: Verify using the address bit argument

The 8085 has a 16-bit address bus. With the upper 3 bits (A15, A14, A13) used for chip select:

Answer:

The $64\text{KB}$ space is divided into $8$ blocks of $8\text{KB}$ each.

Quick Tip:

$n$ upper address bits always yield $2^n$ blocks. With 3 bits: $2^3=8$ blocks. Each block size = Total space $/2^n$.