What is the main advantage of using CMOS technology over NMOS in digital circuits?
Answer: B
CMOS technology uses complementary pairs of transistors resulting in lower static power dissipation and better noise margins compared to NMOS.
Q.182Easy
In a JK flip-flop, what happens when both J and K inputs are 1?
Answer: B
When J=1 and K=1, the JK flip-flop enters toggle mode, changing its state with each clock pulse.
Q.183Easy
A multiplexer with 16 inputs requires how many select lines?
Answer: C
For 2^n inputs, n select lines are needed. For 16 = 2^4 inputs, 4 select lines are required.
Q.184Medium
Which of the following is the correct Boolean expression for De Morgan's Law?
Answer: C
De Morgan's Law states (AB)' = A' + B' and (A+B)' = A'B'. Option C correctly represents one form of this law.
Q.185Medium
What is the propagation delay in a ripple counter compared to a synchronous counter?
Answer: B
Ripple counters have cascading propagation delays as each stage must wait for the previous stage to settle, making them slower than synchronous counters.
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Q.186Medium
In a 4:2 encoder, if input line 5 is active, what is the output?
Answer: C
A 4:2 encoder has 4 inputs and 2 outputs. However, for 8 inputs, a 3:8 encoder or 8:3 decoder is needed. Input line 5 would give binary 101.
Q.187Medium
What is the primary purpose of a Schmitt trigger in digital electronics?
Answer: B
A Schmitt trigger converts analog input to digital output with hysteresis, providing noise immunity and cleaner transitions.
Q.188Medium
In combinational logic design, what is the sum-of-products (SOP) form?
Answer: B
Sum-of-Products form involves taking the AND (product) of variables and then OR (sum) of all such products to form the logic function.
Q.189Medium
What does the term 'fanout' mean in digital logic circuits?
Answer: B
Fanout is the maximum number of gate inputs of the same type that one gate output can reliably drive without degradation.
Q.190Easy
In a 3-bit binary counter, how many clock pulses are needed to complete one full cycle?
Answer: C
A 3-bit counter can count from 000 to 111 (0 to 7 in decimal), requiring 2^3 = 8 clock pulses to complete one full cycle.
Q.191Medium
Which type of latch is transparent when the control signal is HIGH?
Answer: B
A D latch is transparent (passes input to output) when the Enable/Control signal is HIGH, and latches the value when it goes LOW.
Q.192Medium
What is the output frequency of a 4-bit ripple counter when driven by a 16 MHz clock?
Answer: D
In a 4-bit ripple counter, the output frequency of the last stage is f_clock / 2^4 = 16 MHz / 16 = 1 MHz.
Q.193Medium
Which of the following statements about asynchronous reset is TRUE?
Answer: B
Asynchronous reset directly resets the flip-flop without waiting for a clock pulse, providing immediate action regardless of clock state.
Q.194Hard
In a complex digital system, what does 'Setup time' refer to?
Answer: B
Setup time is the minimum duration that the input data must be stable and valid before the active clock edge arrives at the flip-flop.
Q.195Hard
A Moore FSM differs from a Mealy FSM in which aspect?
Answer: B
Moore FSM outputs depend only on current state, while Mealy FSM outputs depend on both current state and current inputs, allowing faster response.
Q.196Hard
What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?
Answer: A
Maximum frequency = 1 / (propagation delay) = 501 ns = 1 / (50 × 10^-9 s) = 20 MHz.
Q.197Hard
In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?
Answer: C
Ideal speedup in pipelining equals the number of pipeline stages. With 5 stages and optimal conditions, speedup is approximately 5x.
Q.198Easy
Which of the following is a non-volatile memory type commonly used in embedded systems?
Answer: C
Flash memory is non-volatile (retains data without power), widely used in embedded systems, SSDs, and microcontrollers as program storage.
Q.199Medium
In a 4-bit synchronous binary counter using JK flip-flops, if the clock frequency is 10 MHz, what is the maximum counting frequency at the MSB output?
Answer: B
In a 4-bit synchronous counter, the MSB output toggles every 2^4 = 16 clock cycles. Therefore, MSB frequency = 10 MHz / 16 = 625 kHz. This is the divide-by-16 behavior of a 4-bit counter.
Q.200Hard
A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?
Answer: C
Using K-map for three variables: (A'BC) + (AB'C) + (ABC') = C(A'B + AB') + ABC' = C(A ⊕ B) + ABC'. This represents XOR operation with an additional term, which is the minimal form requiring fewer gates than other options.
