Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
In a JK flip-flop, when J=1 and K=1, the next state will be:
Answer: C
JK flip-flop truth table: J=1, K=1 causes toggle (Q switches to Q', Q' switches to Q)
Q.542Medium
What is the fan-out of a logic gate?
Answer: B
Fan-out specifies how many standard loads (inputs of similar gates) one output can drive without degradation
Q.543Medium
Which digital logic family has the highest speed of operation?
Answer: C
ECL (Emitter Coupled Logic) has propagation delay ~1ns, fastest among families despite higher power consumption
Q.544Medium
The number of logic levels required to represent 32 different states in binary is:
Answer: B
2^n = 32, therefore n = 5 bits (since 2^5 = 32)
Q.545Medium
What is the main advantage of CMOS logic over TTL?
Answer: B
CMOS technology draws power only during switching, resulting in very low static and dynamic power consumption compared to TTL
Q.546Medium
A 4-to-1 multiplexer has inputs A, B, C, D and select lines S₁, S₀. If S₁=0 and S₀=1, which input is selected?
Answer: B
Selection code 01 (binary) = 1 (decimal), which selects input B (second input)
Q.547Medium
In Karnaugh map simplification, a group of 8 adjacent cells eliminates how many variables?
Answer: C
A group of 2^n cells eliminates n variables. Group of 8 = 2^3, eliminates 3 variables
Q.548Medium
What is the primary function of an encoder in digital electronics?
Answer: C
Encoder produces binary-coded output corresponding to only one active input line among many inputs
Q.549Medium
A synchronous counter differs from asynchronous counter in that:
Answer: B
Synchronous counters apply clock to all flip-flops simultaneously, eliminating propagation delay limitations of asynchronous counters
Q.550Hard
Which of the following Boolean expressions is equivalent to (A+B)·(A+C)?
Answer: A
Using distribution law: (A+B)·(A+C) = A + BC (Consensus theorem verification)
Q.551Hard
In a 3-bit binary counter with initial state 000, after 9 clock pulses, the state will be:
Answer: A
3-bit counter is MOD-8. After 8 pulses it returns to 000, so after 9 pulses state is 001 (counts 0-7, repeats)
Q.552Hard
Design a circuit using NAND gates only to implement NOR function. How many NAND gates are minimum required?
Answer: B
NOR(A,B) = NAND(NAND(A,A), NAND(B,B)). First two gates provide inverted inputs, third performs NAND operation
Q.553Hard
A decade counter counts from 0 to 9. To design a decade counter from a binary counter, how many flip-flops minimum are needed along with additional logic?
Answer: B
4 flip-flops can count 0-15 (MOD-16). With reset logic at count 10, it becomes MOD-10 (decade counter)
Q.554Medium
In a 4-bit ripple counter, the maximum frequency that can be counted is limited by the:
Answer: A
In ripple counters, each flip-flop must settle before the next one can toggle. The maximum countable frequency is limited by the total propagation delay through all stages.
Q.555Easy
Which of the following is a characteristic of combinational circuits?
Answer: B
Combinational circuits have outputs that depend solely on the current input values, with no memory or feedback elements involved.
Q.556Hard
A full adder can be implemented using how many NAND gates minimum?
Answer: C
A full adder requires 9 NAND gates minimum when implemented using NAND gates exclusively to realize the sum and carry outputs.
Q.557Easy
In the 2024-25 examination pattern, which logic family provides the lowest power consumption?
Answer: C
CMOS (Complementary Metal-Oxide-Semiconductor) logic has the lowest power consumption, making it the preferred choice for modern digital systems and portable devices.
Q.558Medium
A 3-to-8 decoder with active-low outputs has how many output lines at logic 0 when the input is 101?
Answer: C
A 3-to-8 decoder with active-low outputs means all lines are 1 except the selected one. Input 101 (5 in decimal) selects line 5, so 7 lines remain at 0.
Q.559Medium
In a Priority encoder, when multiple inputs are high simultaneously, which input gets priority?
Answer: C
Priority encoders can be designed with either highest or lowest priority encoding based on the application requirements specified in the design.
Q.560Easy
The setup time of a flip-flop is defined as:
Answer: B
Setup time is the minimum duration the input data must remain stable and valid before the active clock edge for reliable operation.
