Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
In a Karnaugh map, what does a larger group of adjacent 1's represent?
Answer: B
Larger groups in K-maps represent simplification with fewer variables in the resulting Boolean expression, reducing circuit complexity.
Q.562Medium
A synchronous BCD counter counts from 0000 to 1001, then resets to 0000. This requires modification of a standard 4-bit counter using:
Answer: B
BCD counters use AND gates to detect when the count reaches 1010 (10 in decimal), triggering a reset to 0000 to maintain BCD counting.
Q.563Medium
Which Boolean algebra theorem states that A + A·B = A?
Answer: A
The Absorption theorem simplifies expressions of the form A + A·B to just A, eliminating redundant terms.
Q.564Easy
In a multiplexer, the number of select lines required to select from 16 data inputs is:
Answer: B
For 2^n data inputs, n select lines are needed. 2^4 = 16, so 4 select lines are required for a 16-to-1 multiplexer.
Q.565Medium
The propagation delay in a synchronous counter is:
Answer: A
In synchronous counters, all flip-flops receive the same clock pulse simultaneously, so propagation delay equals one flip-flop delay, not cumulative.
Q.566Easy
Which of the following is used to convert analog signals to digital for processing?
Answer: C
ADCs are specifically designed to convert continuous analog signals into discrete digital representations for digital processing systems.
Q.567Medium
In Quine-McCluskey method, prime implicants are:
Answer: B
Prime implicants are maximal groups of 1's that cannot be combined with other groups, representing the simplest possible terms.
Q.568Easy
A JK flip-flop with J=1, K=1 and clock pulse will:
Answer: C
When both J and K inputs are 1 in a JK flip-flop, the output toggles on the clock pulse, changing from 0 to 1 or 1 to 0.
Q.569Medium
The hold time specification for a flip-flop ensures that:
Answer: A
Hold time is the minimum duration data must remain stable after the clock edge to ensure reliable capture and operation.
Q.570Medium
In a 8-bit parallel-in serial-out (PISO) shift register, how many clock pulses are needed to output all data?
Answer: B
To shift out 8 bits of data serially, 8 clock pulses are required, one for each bit output.
Q.571Medium
Which characteristic distinguishes CMOS gates from TTL gates in practical applications?
Answer: C
CMOS gates consume minimal static power (only during transitions), making them ideal for battery-operated and portable applications.
Q.572Hard
In a Gray code counter, consecutive counts differ by exactly:
Answer: A
Gray code is designed such that consecutive values differ in exactly one bit position, reducing transition errors in digital systems.
Q.573Easy
In a 4-to-1 multiplexer, how many select lines are required?
Answer: B
For a 4-to-1 multiplexer, we need log₂(4) = 2 select lines to choose one of 4 input lines.
Q.574Easy
What is the output of an SR flip-flop when S=1 and R=1 (NOR gate implementation)?
Answer: C
When both S=1 and R=1 in NOR-based SR flip-flop, both outputs become 0, which violates the Q and Q' complementary property, making it an invalid state.
Q.575Easy
Which Boolean theorem states that A + 0 = A and A · 1 = A?
Answer: B
The Identity law in Boolean algebra states that any variable combined with identity element (0 for OR, 1 for AND) remains unchanged.
Q.576Easy
In a ripple counter with 4 flip-flops, what is the maximum count?
Answer: B
A 4-bit counter can count from 0 to 2⁴-1 = 15 (binary: 0000 to 1111), giving a maximum count of 15.
Q.577Easy
What is the primary advantage of CMOS logic over TTL logic in modern designs?
Answer: B
CMOS logic offers significantly lower power consumption (only during switching) and better noise margins compared to TTL, making it ideal for modern low-power applications.
Q.578Medium
In a D flip-flop, the output Q follows the input D on the occurrence of which signal?
Answer: B
A D flip-flop captures the input data on the rising edge of the clock pulse and transfers it to the output Q.
Q.579Medium
Which type of ADC provides the fastest conversion?
Answer: C
Flash ADC uses parallel comparators and provides the fastest conversion as it converts in a single clock pulse, though at higher cost and power consumption.
Q.580Medium
What is the output frequency of a decade counter (MOD-10 counter) when input frequency is 1 MHz?
Answer: A
A decade counter divides the input frequency by 10. Output frequency = 1 MHz ÷ 10 = 100 kHz.
