In a priority encoder, what determines which input is encoded when multiple inputs are active?
Answer: B
Priority encoders are designed with built-in priority logic where the highest priority input (usually MSB) is encoded when multiple inputs are active.
Q.603Medium
What is the main advantage of Gray code over binary code in digital systems?
Answer: B
Gray code ensures only one bit changes between consecutive values, reducing errors in digital transitions and rotary encoders.
Q.604Easy
A 3-to-8 decoder has how many output lines?
Answer: C
A 3-to-8 decoder has 3 input lines and 2^3 = 8 output lines, one for each possible input combination.
Q.605Hard
What is the hold time constraint violation in sequential circuits?
Answer: A
Hold time violation occurs when input data changes before the hold time window after the clock edge, corrupting the captured data.
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Q.606Hard
Which digital logic family provides the best balance between speed and power consumption?
Answer: B
CMOS offers optimal trade-off with low static power dissipation and moderate switching speeds suitable for most applications.
Q.607Hard
In a 4-bit BCD adder, what is the maximum sum that can be represented without requiring correction?
Answer: C
In BCD addition, a result of 18 (binary 10010) requires correction code to convert to valid BCD (1000 + carry). Sums up to 9+9=18 need correction when exceeding 9.
Q.608Hard
What is the primary function of a state machine in digital design?
Answer: B
State machines control digital circuits by transitioning through defined states based on current state, inputs, and clock signals, implementing complex logic sequences.
Q.609Hard
In a 8-bit barrel shifter, how many control bits are required to specify any shift amount?
Answer: B
For an 8-bit barrel shifter, 3 control bits can specify 2^3 = 8 different shift positions (0 to 7), covering all possible shifts.
Q.610Medium
In a synchronous counter design, what is the primary advantage over asynchronous counters?
Answer: B
Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delays that cause glitches in asynchronous designs.
Q.611Easy
Which of the following is the correct relationship for setup time in sequential circuits?
Answer: B
Setup time is the minimum duration that input data must remain stable before the active clock edge for proper capture by the flip-flop.
Q.612Easy
A Karnaugh map with 5 variables requires a minimum of how many cells?
Answer: B
A 5-variable K-map requires 2^5 = 32 cells, typically arranged as two 4x4 grids representing the fifth variable's 0 and 1 states.
Q.613Easy
In a multiplexer circuit, if there are 16 output lines, how many select lines are required?
Answer: B
For n select lines, 2^n output lines are possible. Here 2^4 = 16, so 4 select lines are needed. This is a standard 16:1 multiplexer.
Q.614Medium
Which logic family has the highest noise margin among the following?
Answer: C
CMOS logic has noise margins typically around 30-40% of supply voltage, superior to TTL (~0.4V) and ECL (~0.2V).
Q.615Easy
In a BCD (Binary Coded Decimal) counter, what is the maximum count value?
Answer: A
BCD represents decimal digits 0-9 using 4 bits. A single BCD counter counts from 0 to 9, after which it resets.
Q.616Medium
Which of the following represents the De Morgan's law correctly?
Answer: B
De Morgan's law states: (A.B)' = A'+B' (NAND equals OR of inverted inputs) and (A+B)' = A'.B' (NOR equals AND of inverted inputs).
Q.617Medium
In an SR flip-flop, what happens when both S and R inputs are 1 simultaneously?
Answer: C
When both S=1 and R=1 in SR flip-flop, both Q and Q' become 1, violating the complementary relationship - this is the forbidden state.
Q.618Medium
A Johnson counter (twisted ring counter) with n flip-flops produces how many unique states before repeating?
Answer: B
A Johnson counter with n flip-flops generates 2n unique states (half of the theoretical 2^n), making it useful for decade counters.
Q.619Medium
In FPGA design, what does LUT (Lookup Table) primarily function as?
Answer: B
LUTs in FPGAs are programmable combinational logic blocks that can implement any logic function for inputs (typically 4-6 inputs).
Q.620Medium
What is the Fan-out limit of a TTL gate, and what does it signify?
Answer: B
Fan-out (typically 10 for TTL) is the maximum number of logic gate inputs that an output can reliably drive while maintaining specified voltage levels.
