Electrical Engineering questions for GATE, PSU recruitment and SSC JE draw from network theory, electrical machines, power systems, control systems, measurements and instrumentation, analog and digital electronics, and electromagnetic fields. Numerical answers include the formula used and the unit at each stage, which is where marks are commonly lost even when the approach is correct.
In a multiplexer with 8 input lines, how many output lines are present?
Answer: A
A multiplexer, regardless of the number of inputs, has only one output line. The select lines determine which input is routed to that output.
Q.582Medium
The setup time of a flip-flop is defined as the minimum time during which the input must be stable:
Answer: A
Setup time is the minimum time before the active clock edge during which the input data must remain stable to ensure correct capture.
Q.583Medium
Which of the following logic families has the highest power dissipation?
Answer: B
ECL (Emitter Coupled Logic) has the highest power dissipation among standard logic families but offers excellent speed performance.
Q.584Easy
De Morgan's theorem states that (A·B)' equals:
Answer: A
De Morgan's first theorem states (A·B)' = A' + B'. The complement of AND equals OR of complements.
Q.585Medium
A 16:1 multiplexer requires how many select lines to uniquely identify each input?
Answer: B
For 16 inputs, select lines required = log₂(16) = 4. These 4 lines can produce 2⁴ = 16 unique combinations.
Q.586Medium
In asynchronous (ripple) counters, the propagation delay issue leads to:
Answer: A
In ripple counters, each flip-flop triggers the next, causing cumulative delay. Total delay = n × tₚ, limiting maximum frequency.
Q.587Medium
Which digital circuit is used to convert parallel data into serial form?
Answer: C
A Parallel-In-Serial-Out (PISO) shift register accepts parallel data and outputs it serially, bit by bit.
Q.588Medium
The Boolean expression A·B + A·B' can be simplified to:
Answer: A
A·B + A·B' = A(B + B') = A·1 = A (using factoring and complement law)
Q.589Hard
In a synchronous counter design, all flip-flops receive the clock signal simultaneously. This arrangement primarily eliminates:
Answer: A
Synchronous counters eliminate propagation delay accumulation and race conditions by clocking all flip-flops simultaneously, enabling higher frequency operation.
Q.590Hard
A Schmitt trigger input is used in digital circuits primarily to:
Answer: B
Schmitt trigger provides hysteresis (different thresholds for rising/falling edges), effectively eliminating noise-induced multiple transitions on slowly changing inputs.
Q.591Hard
When implementing a 3-variable Boolean function using a 2-to-1 multiplexer instead of a 8-to-1, one variable must be:
Answer: C
A 2-to-1 MUX has only 1 select line (covering 2 input combinations). For 3 variables (8 combinations), the third variable must be processed through additional logic gates and distributed between select and data paths.
Q.592Easy
A 4-bit binary counter requires how many flip-flops to count from 0 to 15?
Answer: B
A 4-bit counter can represent 2^4 = 16 states (0 to 15), requiring exactly 4 flip-flops.
Q.593Easy
Which logic gate produces a HIGH output only when all inputs are HIGH?
Answer: B
AND gate outputs HIGH only when all inputs are HIGH. This is its fundamental definition.
Q.594Easy
What is the minimum number of NAND gates required to implement a NOT gate?
Answer: A
A single NAND gate with both inputs tied together acts as a NOT gate (inverter).
Q.595Easy
In a J-K flip-flop, when J=1 and K=1, the output will:
Answer: B
When J=1 and K=1, the J-K flip-flop toggles its state on each clock pulse.
Q.596Medium
What is the hold time of a flip-flop?
Answer: A
Hold time is the minimum duration data input must remain stable after the active clock edge.
Q.597Medium
A 32:1 multiplexer can be constructed using how many 4:1 multiplexers?
Answer: B
A 32:1 MUX requires 8 4:1 MUXes in first stage (432=8) and 2 4:1 MUXes in second stage, totaling 10. However, using 6 4:1 MUXes is an efficient hierarchical implementation with proper decoding.
Q.598Medium
Which of the following flip-flops is most suitable for frequency division applications?
Answer: B
T (toggle) flip-flop is ideal for frequency division as it divides input frequency by 2 when toggling.
Q.599Medium
In 2's complement representation, what is the range of numbers for an 8-bit system?
Answer: A
8-bit 2's complement range is from -2^7 to 2^7-1, which is -128 to +127.
Q.600Medium
Which characteristic of CMOS logic makes it suitable for portable devices?
Answer: B
CMOS has minimal static power consumption (only during switching), making it ideal for battery-powered devices.
