Govt. Exams
Entrance Exams
Using K-map for three variables: (A'BC) + (AB'C) + (ABC') = C(A'B + AB') + ABC' = C(A ⊕ B) + ABC'. This represents XOR operation with an additional term, which is the minimal form requiring fewer gates than other options.
Ideal speedup in pipelining equals the number of pipeline stages. With 5 stages and optimal conditions, speedup is approximately 5x.
Maximum frequency = 1 / (propagation delay) = 1 / 50 ns = 1 / (50 × 10^-9 s) = 20 MHz.
Moore FSM outputs depend only on current state, while Mealy FSM outputs depend on both current state and current inputs, allowing faster response.
Setup time is the minimum duration that the input data must be stable and valid before the active clock edge arrives at the flip-flop.
Kogge-Stone is a parallel prefix adder with O(log n) delay compared to Ripple Carry Adder's O(n) linear delay, making it faster for larger bit widths.
More pipeline stages increase throughput (instructions per cycle) but increase latency (clock-to-output delay) due to increased stage delays.
A typical SRAM cell uses 6 transistors: 4 for the cross-coupled latch (2 NMOS + 2 PMOS) and 2 access transistors for read/write operations.
For Hamming code, if 'p' is the number of parity bits, then 2^p ≥ (p + data bits). For 16 data bits: 2^p ≥ p + 16. Testing: 2^5 = 32 ≥ 5 + 16 = 21. ✓
Up/Down counters require multiplexers to select between up and down count logic. Additional XOR/XNOR gates are needed to conditionally modify JK inputs based on control signal C
