Govt. Exams
Entrance Exams
Using K-map for three variables: (A'BC) + (AB'C) + (ABC') = C(A'B + AB') + ABC' = C(A ⊕ B) + ABC'. This represents XOR operation with an additional term, which is the minimal form requiring fewer gates than other options.
In a 4-bit synchronous counter, the MSB output toggles every 2^4 = 16 clock cycles. Therefore, MSB frequency = 10 MHz / 16 = 625 kHz. This is the divide-by-16 behavior of a 4-bit counter.
Flash memory is non-volatile (retains data without power), widely used in embedded systems, SSDs, and microcontrollers as program storage.
Ideal speedup in pipelining equals the number of pipeline stages. With 5 stages and optimal conditions, speedup is approximately 5x.
Maximum frequency = 1 / (propagation delay) = 1 / 50 ns = 1 / (50 × 10^-9 s) = 20 MHz.
Moore FSM outputs depend only on current state, while Mealy FSM outputs depend on both current state and current inputs, allowing faster response.
Setup time is the minimum duration that the input data must be stable and valid before the active clock edge arrives at the flip-flop.
Asynchronous reset directly resets the flip-flop without waiting for a clock pulse, providing immediate action regardless of clock state.
In a 4-bit ripple counter, the output frequency of the last stage is f_clock / 2^4 = 16 MHz / 16 = 1 MHz.
A D latch is transparent (passes input to output) when the Enable/Control signal is HIGH, and latches the value when it goes LOW.
