Govt. Exams
Entrance Exams
A 2-to-1 MUX has only 1 select line (covering 2 input combinations). For 3 variables (8 combinations), the third variable must be processed through additional logic gates and distributed between select and data paths.
Schmitt trigger provides hysteresis (different thresholds for rising/falling edges), effectively eliminating noise-induced multiple transitions on slowly changing inputs.
Synchronous counters eliminate propagation delay accumulation and race conditions by clocking all flip-flops simultaneously, enabling higher frequency operation.
Gray code is designed such that consecutive values differ in exactly one bit position, reducing transition errors in digital systems.
A full adder requires 9 NAND gates minimum when implemented using NAND gates exclusively to realize the sum and carry outputs.
4 flip-flops can count 0-15 (MOD-16). With reset logic at count 10, it becomes MOD-10 (decade counter)
NOR(A,B) = NAND(NAND(A,A), NAND(B,B)). First two gates provide inverted inputs, third performs NAND operation
3-bit counter is MOD-8. After 8 pulses it returns to 000, so after 9 pulses state is 001 (counts 0-7, repeats)
Using distribution law: (A+B)·(A+C) = A + BC (Consensus theorem verification)
