In a network, when using the cut-set method, a cut separates the network into two parts. How many equations are needed for a network with 'b' branches and 'n' nodes to find all branch currents?

The correct answer is B: b - n + 1. Number of independent loop equations needed = b - n + 1 (where b is branches and n is nodes). This represents the circuit's cyclomatic complexity.

What is the primary role of a circuit breaker in a power system?

The correct answer is A: To continuously conduct normal operating current and interrupt fault current automatically. Circuit breakers carry normal load current and automatically open when fault current exceeds preset relay settings, isolating the faulty section.

Which winding in a synchronous motor provides the initial torque for starting?

The correct answer is B: Damper winding. The damper winding (squirrel cage) in a synchronous motor provides the initial asynchronous torque for starting until synchronism is achieved.

Which of the following correctly represents the relationship between the steady-state stability limit and transient stability limit?

The correct answer is B: Transient stability limit > Steady-state stability limit. The transient stability limit is always greater than the steady-state stability limit. A system can maintain transient stability even after a disturbance that would violate steady-state stability.

Design a circuit using NAND gates only to implement NOR function. How many NAND gates are minimum required?

The correct answer is B: 3 gates. NOR(A,B) = NAND(NAND(A,A), NAND(B,B)). First two gates provide inverted inputs, third performs NAND operation

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Electrical Engg (EEE)

Electrical machines, power systems, circuits

123 Q 7 Topics Take Mock Test

Difficulty: All Easy Medium Hard 1–10 of 123

Topics in Electrical Engg (EEE)

All Circuit Analysis 100 Electrical Machines 100 Power Systems 100 Control Systems 100 Power Electronics 100 Electrical Measurements 40 Digital Electronics 100

Q.1 Hard Digital Electronics

What is the setup time requirement for a D flip-flop in a shift register operating at 100 MHz clock frequency?

A Setup time < 10 ns before clock edge

B Setup time < 5 ns before clock edge

C Setup time must be zero

D Setup time depends on manufacturer specifications only

Correct Answer: D. Setup time depends on manufacturer specifications only

EXPLANATION

Setup time is a manufacturer-specified parameter that varies by IC type and technology. At 100 MHz (10 ns period), typical setup times range from 2-5 ns, but exact requirements must be verified from the datasheet. General frequency calculation alone cannot determine setup time.

Test

Q.2 Hard Digital Electronics

In a synchronous counter design using SR flip-flops with Karnaugh map minimization, which hazard is most critical in the implementation?

A Static hazard only

B Dynamic hazard only

C Static and dynamic hazards

D No hazards exist in synchronous design

Correct Answer: C. Static and dynamic hazards

EXPLANATION

Both static hazards (output glitches) and dynamic hazards (multiple transitions) can occur in combinational logic of counter design. Proper K-map grouping and implementation techniques are needed to minimize them.

Test

Q.3 Hard Digital Electronics

In the context of digital signal processing, what is the Nyquist sampling theorem's requirement?

A Sampling frequency must be equal to signal frequency

B Sampling frequency must be at least twice the highest frequency component of the signal

C Sampling frequency must be half the signal frequency

D Sampling frequency has no relationship with signal frequency

Correct Answer: B. Sampling frequency must be at least twice the highest frequency component of the signal

EXPLANATION

Nyquist theorem states fs ≥ 2×fmax to avoid aliasing. Sampling below this rate causes frequency components to fold back and corrupt the signal.

Test

Q.4 Hard Digital Electronics

In asynchronous sequential circuits, what is the primary concern regarding state transitions?

A Clock skew

B Race conditions and hazards that may cause incorrect state transitions

C Excessive power consumption

D Limited state count

Correct Answer: B. Race conditions and hazards that may cause incorrect state transitions

EXPLANATION

Asynchronous circuits lack global clock, so multiple state variables can change simultaneously, causing race conditions and hazards if not carefully designed.

Test

Q.5 Hard Digital Electronics

In a sequential logic circuit, metastability occurs when the input changes relative to the clock edge. How can this be minimized?

A Increasing clock frequency

B Using synchronizer flip-flops (cascaded D flip-flops)

C Decreasing gate delays

D Using combinational circuits only

Correct Answer: B. Using synchronizer flip-flops (cascaded D flip-flops)

EXPLANATION

Synchronizer circuits use cascaded flip-flops to provide settling time between asynchronous signal and sampling clock, reducing metastability risk.

Test

Q.6 Hard Digital Electronics

In a 8-bit barrel shifter, how many control bits are required to specify any shift amount?

A 2 bits

B 3 bits

C 4 bits

D 8 bits

Correct Answer: B. 3 bits

EXPLANATION

For an 8-bit barrel shifter, 3 control bits can specify 2^3 = 8 different shift positions (0 to 7), covering all possible shifts.

Test

Q.7 Hard Digital Electronics

What is the primary function of a state machine in digital design?

A Amplify digital signals

B Sequence through predefined states based on inputs and clock

C Convert analog signals to digital

D Store large amounts of data

Correct Answer: B. Sequence through predefined states based on inputs and clock

EXPLANATION

State machines control digital circuits by transitioning through defined states based on current state, inputs, and clock signals, implementing complex logic sequences.

Test

Q.8 Hard Digital Electronics

In a 4-bit BCD adder, what is the maximum sum that can be represented without requiring correction?

A 9

B 15

C 18

D 19

Correct Answer: C. 18

EXPLANATION

In BCD addition, a result of 18 (binary 10010) requires correction code to convert to valid BCD (1000 + carry). Sums up to 9+9=18 need correction when exceeding 9.

Test

Q.9 Hard Digital Electronics

Which digital logic family provides the best balance between speed and power consumption?

A TTL

B CMOS

C ECL

D PMOS

Correct Answer: B. CMOS

EXPLANATION

CMOS offers optimal trade-off with low static power dissipation and moderate switching speeds suitable for most applications.

Test

Q.10 Hard Digital Electronics

What is the hold time constraint violation in sequential circuits?

A Data changes before the hold time interval ends

B Clock frequency exceeds maximum operating frequency

C Multiple flip-flops receive different clock signals

D Reset signal applied incorrectly

Correct Answer: A. Data changes before the hold time interval ends

EXPLANATION

Hold time violation occurs when input data changes before the hold time window after the clock edge, corrupting the captured data.

Test

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