Govt. Exams
Entrance Exams
Setup time is a manufacturer-specified parameter that varies by IC type and technology. At 100 MHz (10 ns period), typical setup times range from 2-5 ns, but exact requirements must be verified from the datasheet. General frequency calculation alone cannot determine setup time.
Both static hazards (output glitches) and dynamic hazards (multiple transitions) can occur in combinational logic of counter design. Proper K-map grouping and implementation techniques are needed to minimize them.
Nyquist theorem states fs ≥ 2×fmax to avoid aliasing. Sampling below this rate causes frequency components to fold back and corrupt the signal.
Asynchronous circuits lack global clock, so multiple state variables can change simultaneously, causing race conditions and hazards if not carefully designed.
Synchronizer circuits use cascaded flip-flops to provide settling time between asynchronous signal and sampling clock, reducing metastability risk.
For an 8-bit barrel shifter, 3 control bits can specify 2^3 = 8 different shift positions (0 to 7), covering all possible shifts.
State machines control digital circuits by transitioning through defined states based on current state, inputs, and clock signals, implementing complex logic sequences.
In BCD addition, a result of 18 (binary 10010) requires correction code to convert to valid BCD (1000 + carry). Sums up to 9+9=18 need correction when exceeding 9.
CMOS offers optimal trade-off with low static power dissipation and moderate switching speeds suitable for most applications.
Hold time violation occurs when input data changes before the hold time window after the clock edge, corrupting the captured data.
