Govt. Exams
Entrance Exams
When J=1 and K=1, the JK flip-flop enters toggle mode, changing its state with each clock pulse.
In RAM notation m×n, m represents number of addressable locations and n represents bits per location.
Full adder: A+B+Cin = 1+1+1 = 3 (binary 11). Sum = 1, Carry out = 1.
In a D flip-flop, Q takes the value of D on the clock edge. When D = 1, Q becomes 1 and Q' becomes 0.
DRAM (Dynamic RAM) is volatile and requires periodic refreshing. Data is lost without power, unlike non-volatile memories like ROM, EEPROM, and Flash.
Parity bits are used for error detection by tracking whether the number of 1s in data is even or odd.
For 2^n inputs, n select lines are needed. For 8 inputs, log₂(8) = 3 select lines.
NAND gate is the complement of AND, so Y = (A.B)' where . represents AND operation.
XOR (Exclusive OR) produces 1 when inputs are different and 0 when they are same.
Binary 101 = 5 in decimal, so output line 5 is activated in a decoder.