Govt. Exams
Entrance Exams
Loop gain = Aβ, where A is open-loop gain and β is feedback fraction. For stability, loop gain should be <1 for phase margin requirements.
Lower cutoff frequency fL ≈ 1/(2π·CC·Rin) where CC is coupling capacitor and Rin is input impedance. Larger CC gives lower fL.
The -3dB cutoff frequency is where the magnitude of gain reduces to 1/√2 (≈ 70.7%) of maximum gain. This defines the bandwidth of the amplifier.
CC amplifier has very high input impedance (Zin ≈ β·re) making it suitable as a buffer stage between high impedance sources and low impedance loads.
CMRR = Ad/Ac, where Ad is differential mode gain and Ac is common mode gain. High CMRR (>80dB typical) is desired to reject common mode noise.
Emitter degeneration without bypass capacitor increases input impedance and reduces gain but significantly increases bandwidth due to negative feedback.
In a 4-bit synchronous counter, the MSB output toggles every 2^4 = 16 clock cycles. Therefore, MSB frequency = 10 MHz / 16 = 625 kHz. This is the divide-by-16 behavior of a 4-bit counter.
Asynchronous reset directly resets the flip-flop without waiting for a clock pulse, providing immediate action regardless of clock state.
In a 4-bit ripple counter, the output frequency of the last stage is f_clock / 2^4 = 16 MHz / 16 = 1 MHz.
A D latch is transparent (passes input to output) when the Enable/Control signal is HIGH, and latches the value when it goes LOW.
