What is the phase shift introduced by a first-order RC low-pass filter at the cutoff frequency (fc)?

The correct answer is B: -45°. At cutoff frequency, the impedances of R and C are equal, resulting in a phase shift of -45° for a single RC low-pass filter.

A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?

The correct answer is C: Y = C(A ⊕ B) + ABC'. Using K-map for three variables: (A'BC) + (AB'C) + (ABC') = C(A'B + AB') + ABC' = C(A ⊕ B) + ABC'. This represents XOR operation with an additional term, which is the minimal form requiring fewer gates than other options.

In a BJT operating in the active region, which relationship holds true?

The correct answer is B: VBE ≈ 0.7V and VCE > VCE(sat). Active region requires base-emitter junction forward biased (~0.7V) and collector-base reverse biased (VCE > saturation voltage).

In a p-n junction diode, the depletion width increases when:

The correct answer is A: Reverse bias voltage increases. Reverse bias widens the depletion region by pulling majority carriers away from the junction, increasing the width of the space charge region.

What is the relationship between collector current (Ic) and base current (Ib) in a BJT?

The correct answer is A: Ic = Ib × β (beta). In BJT, the current gain (beta or hFE) is defined as the ratio of collector current to base current: β = Ic/Ib, so Ic = Ib × β. Beta typically ranges from 50 to 500 for most transistors.

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Electronics (ECE)

Analog/digital electronics, communication

187 Q 4 Topics Take Mock Test

Difficulty: All Easy Medium Hard 111–120 of 187

Topics in Electronics (ECE)

All Electronic Devices 100 Digital Electronics 100 Analog Circuits 100 Signals & Systems 100

Q.111 Medium Digital Electronics

In a synchronous counter design, what is the main advantage over an asynchronous counter?

A Lower power consumption

B Elimination of timing skew and glitches

C Simpler circuit design

D Requires fewer flip-flops

Correct Answer: B. Elimination of timing skew and glitches

EXPLANATION

Synchronous counters have all flip-flops clocked simultaneously, eliminating propagation delay issues and glitches present in asynchronous counters.

Test

Q.112 Medium Digital Electronics

How many AND gates are required to implement a 3:8 decoder?

A 3 AND gates

B 6 AND gates

C 8 AND gates

D 4 AND gates

Correct Answer: C. 8 AND gates

EXPLANATION

A 3:8 decoder has 8 output lines, and each requires one AND gate (with appropriate inversions of inputs).

Test

Q.113 Medium Digital Electronics

In Booth's algorithm for multiplication, what is the purpose of examining the last two bits (current and previous)?

A To determine if addition or subtraction is needed

B To identify potential overflow conditions

C To check for parity errors

D To initialize the accumulator

Correct Answer: A. To determine if addition or subtraction is needed

EXPLANATION

Booth's algorithm examines consecutive bits to reduce the number of addition operations by detecting transitions from 0 to 1 and 1 to 0.

Test

Q.114 Medium Digital Electronics

In a 4-bit Binary Weighted DAC, what is the weight of the MSB compared to the LSB?

A 2 times

B 4 times

C 8 times

D 16 times

Correct Answer: C. 8 times

EXPLANATION

For a 4-bit DAC, MSB weight = 2^(4-1) = 8 times the LSB weight.

Test

Q.115 Medium Digital Electronics

In a Mealy state machine, the output depends on which of the following?

A Present state only

B Present state and present input

C Previous state only

D Clock signal only

Correct Answer: B. Present state and present input

EXPLANATION

Mealy machines have outputs dependent on both current state and current input, unlike Moore machines which depend only on state.

Test

Q.116 Medium Digital Electronics

What is the maximum frequency of operation for a JK flip-flop with setup time 5ns, hold time 3ns, and propagation delay 8ns?

A 62.5 MHz

B 83.3 MHz

C 125 MHz

D 100 MHz

Correct Answer: C. 125 MHz

EXPLANATION

Maximum frequency = 1/(setup time + propagation delay) = 1/(5+3)ns = 1/8ns = 125 MHz.

Test

Q.117 Medium Digital Electronics

What is the main advantage of a Carry Lookahead Adder (CLA) over a Ripple Carry Adder (RCA)?

A Lower cost

B Reduced propagation delay and faster operation

C Simpler design

D Lower power consumption

Correct Answer: B. Reduced propagation delay and faster operation

EXPLANATION

CLA reduces propagation delay from O(n) to O(log n) by calculating carry signals in parallel, making it much faster than RCA.

Test

Q.118 Medium Digital Electronics

A 4-bit Ripple Carry Adder has a total propagation delay of 12 ns. If each full adder stage has a propagation delay of 3 ns, what is the delay for carry propagation?

A 3 ns

B 9 ns

C 12 ns

D 15 ns

Correct Answer: B. 9 ns

EXPLANATION

In a 4-bit ripple carry adder, the carry must propagate through 3 stages (from FA1 to FA4), giving delay = 3 × 3 ns = 9 ns.

Test

Q.119 Medium Digital Electronics

A 32×8 ROM has how many address lines and data lines respectively?

A 5 address lines, 8 data lines

B 8 address lines, 5 data lines

C 10 address lines, 8 data lines

D 32 address lines, 8 data lines

Correct Answer: A. 5 address lines, 8 data lines

EXPLANATION

For 32 memory locations, we need log2(32) = 5 address lines. The data width is 8 bits, hence 8 data lines.

Test

Q.120 Medium Digital Electronics

In Gray code, how many bits change when transitioning from 5 (0101) to 6 (0110)?

A 1 bit

B 2 bits

C 3 bits

D 4 bits

Correct Answer: A. 1 bit

EXPLANATION

Gray code for 5 is 0111 and for 6 is 0101. Only 1 bit changes between consecutive numbers, which is the main advantage of Gray code.

Test

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