Govt. Exams
Entrance Exams
2's complement subtraction (A-B) converts to addition A+2's complement of B. This requires 4 full adders (for addition) and XOR gates (for bit complementing), avoiding dedicated subtractors
An n-variable Boolean function can be efficiently implemented using a 2ⁿ-to-1 multiplexer where variables form select lines and minterms form data inputs, achieving minimal gate implementation
For modulo-N counter, minimum flip-flops required = ⌈log₂(N)⌉. For modulo-6: ⌈log₂(6)⌉ = ⌈2.58⌉ = 3 flip-flops (counts 0-5)
Setup time (tsu) is the minimum duration the input signal must remain stable and valid before the active clock edge for reliable capture and state change
Booth's algorithm replaces consecutive 1s with a single subtraction and addition operation. Consecutive 1s (like 0111) are treated as 1000-1, reducing computation steps compared to processing each 1 individually
Synchronous counters clock all flip-flops simultaneously, eliminating propagation delay problems. This allows higher operating frequencies without cumulative timing errors present in ripple counters
Mealy machine output depends on both present state and present input. Moore machine output depends only on present state. Mealy machines are more efficient.
An n-bit counter has 2^n possible states (from 0 to 2^n - 1). For 3-bit counter: states are 0 to 7 (000 to 111).
In synchronous counters, all flip-flops change simultaneously, so maximum frequency is determined by one flip-flop delay. f_max = 1/t_pd = 1/10ns = 100 MHz.
A 4-variable K-map has 2^4 = 16 cells, each representing one minterm. To cover all minterms, minimum 16 cells are needed.
