Govt. Exams
Entrance Exams
De Morgan's law states: (A.B)' = A'+B' (NAND equals OR of inverted inputs) and (A+B)' = A'.B' (NOR equals AND of inverted inputs).
CMOS logic has noise margins typically around 30-40% of supply voltage, superior to TTL (~0.4V) and ECL (~0.2V).
Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delays that cause glitches in asynchronous designs.
Gray code ensures only one bit changes between consecutive values, reducing errors in digital transitions and rotary encoders.
Priority encoders are designed with built-in priority logic where the highest priority input (usually MSB) is encoded when multiple inputs are active.
4GB = 4 × 2^30 bytes = 2^32 bytes. Therefore, 32 address lines are needed (2^32 addresses).
CMOS has minimal static power consumption (only during switching), making it ideal for battery-powered devices.
8-bit 2's complement range is from -2^7 to 2^7-1, which is -128 to +127.
T (toggle) flip-flop is ideal for frequency division as it divides input frequency by 2 when toggling.
A 32:1 MUX requires 8 4:1 MUXes in first stage (32/4=8) and 2 4:1 MUXes in second stage, totaling 10. However, using 6 4:1 MUXes is an efficient hierarchical implementation with proper decoding.
