Govt. Exams
Entrance Exams
CMOS gates consume minimal static power (only during transitions), making them ideal for battery-operated and portable applications.
To shift out 8 bits of data serially, 8 clock pulses are required, one for each bit output.
Hold time is the minimum duration data must remain stable after the clock edge to ensure reliable capture and operation.
Prime implicants are maximal groups of 1's that cannot be combined with other groups, representing the simplest possible terms.
In synchronous counters, all flip-flops receive the same clock pulse simultaneously, so propagation delay equals one flip-flop delay, not cumulative.
The Absorption theorem simplifies expressions of the form A + A·B to just A, eliminating redundant terms.
BCD counters use AND gates to detect when the count reaches 1010 (10 in decimal), triggering a reset to 0000 to maintain BCD counting.
Priority encoders can be designed with either highest or lowest priority encoding based on the application requirements specified in the design.
A 3-to-8 decoder with active-low outputs means all lines are 1 except the selected one. Input 101 (5 in decimal) selects line 5, so 7 lines remain at 0.
In ripple counters, each flip-flop must settle before the next one can toggle. The maximum countable frequency is limited by the total propagation delay through all stages.
