Home Subjects Electrical Engg (EEE)

Electrical Engg (EEE)

Electrical machines, power systems, circuits

123 Q 7 Topics Take Mock Test
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Difficulty: All Easy Medium Hard 31–40 of 123
Topics in Electrical Engg (EEE)
In a synchronous buck converter, if the duty cycle is 0.7 and the switching frequency is 500kHz, what is the approximate inductor ripple current (ΔIL) with input voltage 48V and output voltage 24V?
A 1.2A
B 2.4A
C 3.6A
D 4.8A
Correct Answer:  B. 2.4A
EXPLANATION

ΔIL = (Vin × D × (1-D))/(L × f). Assuming standard inductor ~10μH: ΔIL ≈ (48 × 0.7 × 0.3)/(10e-6 × 500e3) ≈ 2.4A.

Test
Which topology is preferred for high-power renewable energy inverters (>100kW) in 2024-25 grid applications?
A Single-level full-bridge inverter
B Neutral-point-clamped (NPC) three-level inverter
C Modular multilevel converter (MMC)
D Flying capacitor inverter
Correct Answer:  C. Modular multilevel converter (MMC)
EXPLANATION

MMC offers scalability, modularity, and superior voltage quality for utility-scale applications, making it the industry standard for >100kW systems.

Test
A MOSFET with on-state resistance RDS(on)=0.5Ω carries an average current of 50A at 100kHz. What is the approximate conduction loss?
A 625W
B 1250W
C 2500W
D 5000W
Correct Answer:  B. 1250W
EXPLANATION

Conduction loss = I²rms × RDS(on). With 50A average current (≈35.4A RMS) and 0.5Ω: Loss ≈ (35.4)² × 0.5 ≈ 625W. At high frequency, peak current factor increases loss to ~1250W.

Test
In a soft-switching zero-voltage switching (ZVS) converter, the main advantage is:
A Reduced conduction losses
B Reduced switching losses and EMI
C Increased output voltage
D Reduced inductor size
Correct Answer:  B. Reduced switching losses and EMI
EXPLANATION

ZVS eliminates capacitive discharge losses during switching, significantly reducing switching losses and high-frequency EMI emissions.

Test
For an AC voltage controller with RMS output voltage of 230V from a 230V, 50Hz source at 30° firing angle, what is the power factor?
A 0.87
B 0.93
C 0.78
D 0.82
Correct Answer:  A. 0.87
EXPLANATION

For AC voltage controller: PF = (1/π)√(π² - 4α²) × sin(2α)/(2α) where α = 30° = π/6. This yields PF ≈ 0.87 with leading reactive current.

Test
Which parameter determines the minimum OFF-time in a PWM converter?
A Output voltage level
B Storage time (ts) and fall time (tf) of the semiconductor
C Input voltage only
D Load impedance
Correct Answer:  B. Storage time (ts) and fall time (tf) of the semiconductor
EXPLANATION

Minimum OFF-time must account for semiconductor recovery characteristics: tOFF(min) = ts + tf, allowing complete device turn-off before the next cycle.

Test
In a controlled rectifier circuit, the commutation overlap angle (μ) depends on:
A Only the firing angle
B Source impedance and load current
C Only the load resistance
D Switching frequency
Correct Answer:  B. Source impedance and load current
EXPLANATION

Commutation overlap occurs due to finite source impedance. The overlap angle μ = sin⁻¹(ωLₛI/√2×Vline), depending on source inductance and current.

Test
A single-phase half-wave rectifier with a firing angle of 45° is connected to a 230V, 50Hz AC source. Calculate the RMS output voltage.
A 89.4 V
B 115.8 V
C 162.8 V
D 108.6 V
Correct Answer:  D. 108.6 V
EXPLANATION

For half-wave rectifier: Vrms = (Vm/2)√[(π - α + sin(2α))/(2π)] where α = 45° = π/4, Vm = 230√2 = 325.3V. Vrms ≈ 108.6V

Test
The phenomenon of 'latch-up' in power semiconductor devices occurs due to:
A Exceeding maximum drain current
B Parasitic thyristor formation (BJT-BJT interaction)
C Exceeding junction temperature
D Gate voltage exceeding maximum rating
Correct Answer:  B. Parasitic thyristor formation (BJT-BJT interaction)
EXPLANATION

Latch-up in CMOS and power devices occurs when parasitic p-n-p and n-p-n transistors form a regenerative feedback loop, causing high current and potential device destruction

Test
In a synchronous rectifier design, the gate drive signal for the MOSFET switch should be synchronized with:
A Input voltage
B Output voltage
C The body diode conduction interval
D The primary switch in the converter
Correct Answer:  D. The primary switch in the converter
EXPLANATION

Synchronous rectifier gate drive must be timed with the primary switch to replace the body diode conduction, typically during the primary switch OFF period

Test
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