Govt. Exams
Entrance Exams
CLA reduces propagation delay from O(n) to O(log n) by calculating carry signals in parallel, making it much faster than RCA.
In a 4-bit ripple carry adder, the carry must propagate through 3 stages (from FA1 to FA4), giving delay = 3 × 3 ns = 9 ns.
For 32 memory locations, we need log2(32) = 5 address lines. The data width is 8 bits, hence 8 data lines.
Gray code for 5 is 0111 and for 6 is 0101. Only 1 bit changes between consecutive numbers, which is the main advantage of Gray code.
In a 3-to-8 decoder with active low enable and select lines = 000, only output 0 is activated (becomes 0), while all others remain 1.
Setup time (t_su) is the minimum duration that the input signal must be stable and valid before the active clock edge for reliable operation.
The carry output of a full adder is: C_out = (A·B) + (B·C_in) + (A·C_in), which requires both AND and OR gates.
A Johnson counter (twisted ring counter) has a sequence length of 2n, where n is the number of flip-flops. For 4 flip-flops: 2×4 = 8 states.
In synchronous counters, all flip-flops are clocked simultaneously, so the maximum frequency is limited only by the propagation delay of a single flip-flop, not the cumulative delay.
For N states, minimum flip-flops required = ⌈log₂(N)⌉. For 7 states: ⌈log₂(7)⌉ = ⌈2.807⌉ = 3 flip-flops (can represent 2³=8 states)
