Govt. Exams
Entrance Exams
Gray Code changes only one bit between consecutive numbers, minimizing transition errors. This prevents multiple simultaneous bit transitions that could cause undefined intermediate states
Two cascaded 4-bit counters form an 8-bit counter system. Maximum count = 2⁸ - 1 = 255 (counts from 0 to 255, total 256 states)
Hold time (th) is the minimum duration input must remain stable after the clock edge. Violation can cause metastability—a state where flip-flop output is uncertain or oscillates unpredictably
A magnitude comparator produces exactly 3 mutually exclusive outputs: A>B (1,0,0) or A=B (0,1,0) or A<B (0,0,1). These are the only 3 possible comparison results for any input pair
2's complement subtraction (A-B) converts to addition A+2's complement of B. This requires 4 full adders (for addition) and XOR gates (for bit complementing), avoiding dedicated subtractors
An n-variable Boolean function can be efficiently implemented using a 2ⁿ-to-1 multiplexer where variables form select lines and minterms form data inputs, achieving minimal gate implementation
For modulo-N counter, minimum flip-flops required = ⌈log₂(N)⌉. For modulo-6: ⌈log₂(6)⌉ = ⌈2.58⌉ = 3 flip-flops (counts 0-5)
Setup time (tsu) is the minimum duration the input signal must remain stable and valid before the active clock edge for reliable capture and state change
Booth's algorithm replaces consecutive 1s with a single subtraction and addition operation. Consecutive 1s (like 0111) are treated as 1000-1, reducing computation steps compared to processing each 1 individually
Synchronous counters clock all flip-flops simultaneously, eliminating propagation delay problems. This allows higher operating frequencies without cumulative timing errors present in ripple counters
