Govt. Exams
Entrance Exams
Hold time is the minimum duration data input must remain stable after the active clock edge.
A·B + A·B' = A(B + B') = A·1 = A (using factoring and complement law)
A Parallel-In-Serial-Out (PISO) shift register accepts parallel data and outputs it serially, bit by bit.
In ripple counters, each flip-flop triggers the next, causing cumulative delay. Total delay = n × tₚ, limiting maximum frequency.
For 16 inputs, select lines required = log₂(16) = 4. These 4 lines can produce 2⁴ = 16 unique combinations.
ECL (Emitter Coupled Logic) has the highest power dissipation among standard logic families but offers excellent speed performance.
Setup time is the minimum time before the active clock edge during which the input data must remain stable to ensure correct capture.
A decade counter divides the input frequency by 10. Output frequency = 1 MHz ÷ 10 = 100 kHz.
Flash ADC uses parallel comparators and provides the fastest conversion as it converts in a single clock pulse, though at higher cost and power consumption.
A D flip-flop captures the input data on the rising edge of the clock pulse and transfers it to the output Q.
