In a Wheatstone bridge for resistance measurement, if R₁ = 100 Ω, R₂ = 50 Ω, R₃ = 200 Ω, what should be R₄ for balance?

The correct answer is B: 100 Ω. At balance: R₁/R₂ = R₃/R₄; R₄ = (R₂ × R₃)/R₁ = (50 × 200)/100 = 100 Ω.

In a Wheat stone bridge, the null deflection is obtained when the ratio of resistances satisfies which condition?

The correct answer is B: R₁ × R₄ = R₂ × R₃. At balance condition in Wheatstone bridge: R₁/R₂ = R₃/R₄, which can be rearranged to R₁ × R₄ = R₂ × R₃

Which of the following is NOT a component of the Indian National Load Despatch Centre (NLDC)?

The correct answer is C: Direct transmission line maintenance. NLDC coordinates scheduling and operation but does not directly maintain transmission lines. That responsibility lies with POWERGRID.

The Q-factor (quality factor) of a resonant circuit is defined as:

The correct answer is C: Q = ω₀L/R or 1/(ω₀RC). Q-factor represents selectivity and bandwidth characteristics. For series RLC: Q = ω₀L/R = 1/(ω₀RC) = (1/R)√(L/C).

In a state-space representation, if the system has 4 state variables, what is the dimension of the state vector?

The correct answer is C: 4. The state vector x(t) contains all state variables. With 4 state variables, it's a 4×1 column vector, so the dimension is 4.

Home

Home › Subjects › Electrical Engg (EEE)

Electrical Engg (EEE)

Electrical machines, power systems, circuits

321 Q 7 Topics Take Mock Test

Difficulty: All Easy Medium Hard 41–50 of 321

Topics in Electrical Engg (EEE)

All Circuit Analysis 100 Electrical Machines 100 Power Systems 100 Control Systems 100 Power Electronics 100 Electrical Measurements 40 Digital Electronics 100

Q.41 Medium Digital Electronics

A synchronous counter differs from asynchronous counter in that:

A It uses more flip-flops

B All flip-flops receive same clock pulse simultaneously

C It has lower frequency limitation

D It requires no clock signal

Correct Answer: B. All flip-flops receive same clock pulse simultaneously

EXPLANATION

Synchronous counters apply clock to all flip-flops simultaneously, eliminating propagation delay limitations of asynchronous counters

Test

Q.42 Medium Digital Electronics

What is the primary function of an encoder in digital electronics?

A Convert analog to digital signals

B Convert decimal to binary

C Convert active input lines into coded output

D Amplify weak signals

Correct Answer: C. Convert active input lines into coded output

EXPLANATION

Encoder produces binary-coded output corresponding to only one active input line among many inputs

Test

Q.43 Medium Digital Electronics

In Karnaugh map simplification, a group of 8 adjacent cells eliminates how many variables?

A 1 variable

B 2 variables

C 3 variables

D 4 variables

Correct Answer: C. 3 variables

EXPLANATION

A group of 2^n cells eliminates n variables. Group of 8 = 2^3, eliminates 3 variables

Test

Q.44 Medium Digital Electronics

A 4-to-1 multiplexer has inputs A, B, C, D and select lines S₁, S₀. If S₁=0 and S₀=1, which input is selected?

A A

B B

C C

D D

Correct Answer: B. B

EXPLANATION

Selection code 01 (binary) = 1 (decimal), which selects input B (second input)

Test

Q.45 Medium Digital Electronics

What is the main advantage of CMOS logic over TTL?

A Higher speed

B Lower power consumption

C Better noise immunity

D Lower cost

Correct Answer: B. Lower power consumption

EXPLANATION

CMOS technology draws power only during switching, resulting in very low static and dynamic power consumption compared to TTL

Test

Q.46 Medium Digital Electronics

The number of logic levels required to represent 32 different states in binary is:

A 4 bits

B 5 bits

C 6 bits

D 7 bits

Correct Answer: B. 5 bits

EXPLANATION

2^n = 32, therefore n = 5 bits (since 2^5 = 32)

Test

Q.47 Medium Digital Electronics

Which digital logic family has the highest speed of operation?

A CMOS

B TTL

C ECL

D NMOS

Correct Answer: C. ECL

EXPLANATION

ECL (Emitter Coupled Logic) has propagation delay ~1ns, fastest among families despite higher power consumption

Test

Q.48 Medium Digital Electronics

What is the fan-out of a logic gate?

A Maximum number of inputs it can have

B Maximum number of standard loads it can drive

C Propagation delay through the gate

D Power consumption of the gate

Correct Answer: B. Maximum number of standard loads it can drive

EXPLANATION

Fan-out specifies how many standard loads (inputs of similar gates) one output can drive without degradation

Test

Q.49 Medium Digital Electronics

In a JK flip-flop, when J=1 and K=1, the next state will be:

A Set to 1

B Reset to 0

C Toggle

D No change

Correct Answer: C. Toggle

EXPLANATION

JK flip-flop truth table: J=1, K=1 causes toggle (Q switches to Q', Q' switches to Q)

Test

Q.50 Medium Digital Electronics

Which of the following is a sequential logic circuit?

A Multiplexer

B Decoder

C Flip-flop

D Encoder

Correct Answer: C. Flip-flop

EXPLANATION

Flip-flops are sequential logic circuits with memory; others are combinational circuits without memory

Test

1…3 4 5 6 7…33

All Subjects & Topics

Govt. Exams

Entrance Exams

Teacher Exams

Subjects

Quick Links

Electrical Engg (EEE)